Architecture for a communications device

ABSTRACT

The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority of U.S. Provisional PatentApplication Serial No. 60/233369, which was filed Sep. 18, 2000, U.S.patent application Ser. No. ______ entitled “Method and Apparatus forPath Metric Processing in Telecommunications Systems” filed on even dateherewith (inventor Bickerstaff; Attorney Ref: Bickerstaff 3), and U.S.patent application Ser. No. ______ entitled “Butterfly Processor forTelecommunications” filed on even date herewith (inventors Nicol,Bickerstaff, and Xu; Attorney Ref: Bickerstaff 2-19-3).

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to wirelesscommunications and, in particular, to a decoder architecture forwireless communications systems.

BACKGROUND ART

[0003] Communication systems deal with the transmission of informationfrom a transmitter to a receiver. The transmission medium through whichthe information passes often contains many sources of noise, includingcosmic radiation, Additive White Gaussian Noise (AWGN), Rayleighscattering (multipath propagation) and electromagnetic noise. Thepresence of these noise sources corrupts or prevents the transmission ofthe desired information, thus limiting the ability to communicate.

[0004] It is well known in the art that coding of the information to betransmitted, through the addition of redundant information calculatedfrom the source information, improves the ability to successfullyreceive the transmitted information. Decoding uses the redundantinformation to detect the presence of errors or estimate the mostprobable emitted bits, given those received. Errors are detected whenthe transmitted redundancy is different from that subsequentlycalculated with the received data.

[0005] The weight of a codeword is a measure of the capacity to recoverdata from the codeword. A codeword with a high number of bits has a highweight. A low weight codeword exhibits a low ability to recover data,whereas, conversely, a high weight codeword exhibits improved recoveryof data.

[0006] Automatic-repeat-request (ARQ) coding schemes employ anerror-detection code. If the presence of an error is detected in theinformation received, a message requesting retransmission of therelevant information is sent from the receiver to the transmitter. ARQcoding schemes are relatively simple, but require the use of a feedbackchannel and deliver variable and comparatively slow throughput.

[0007] Forward error correction (FEC) coding schemes are used to encodeinformation in systems in which propagation delays and latency are ofconcern. The receiver is able to detect and correct errors, withoutrequiring a feedback channel.

[0008] Coding schemes can be broadly categorised into block codes andconvolutional codes.

[0009] Block codes map a message of k information bits into a structuredsequence of n bits, where n>k. The code is referred to as a (n,k) code.The ratio (n−k)/k is called the redundancy of the code and the ratio ofinformation bits to the total number of bits, k/n, is called the coderate. The extra bits inserted provide redundancy and are used by thedecoder to provide error detection and correction. The redundant bitsadded during encoding are only dependent on the k information bits inthe message block. Block codes are often used to detect errors when ARQis implemented.

[0010] Convolutional encoding generates a block of n code bits in agiven period of time from k information bits, where n and k aretypically small. The block of n bits generated by the encoder isdependent not only on the k information bits of the time period, butalso on the message blocks generated during a predefined number ofpreceding time periods. The memory thus imparted on the coding enableserrors to be corrected based on allowable sequences of codes.Convolutional decoding may be performed using either a Viterbi algorithmor LogMAP algorithm.

[0011] Convolutional codes are preferred for wireless voicecommunications systems in which the retransmission of data and itsassociated delay is intolerable. Block codes are capable of deliveringhigher throughput and are preferred for the transmission of data wherelatency is less of a concern.

[0012] Turbo codes, also known as parallel concatenated codes, are aclass of codes whose performance is very close to the Shannon capacitylimit. Turbo coders are implemented by connecting convolutional encoderseither in parallel or series to produce concatenated outputs. Bitsequences passing from one encoder to another are permuted by aninterleaver. In this manner, low-weight code words produced by a singleencoder are transformed into high-weight code words. Turbo decoding thustakes two low weight codewords and obtains the effect of a much higherweight codeword.

[0013] At present, consumer wireless communication systems are primarilyconcerned with the transmission of voice. Such wireless communicationsystems include Advanced Mobile Phone Service (AMPS), Global System forMobile Communication (GSM) and Code Division Multiple Access (CDMA).These represent the first (IG) and second (2G) generation systems. Withthe convergence of data and voice communication systems, thesecond-and-a-half generation (2.5G) and third generation (3G) systemsare emerging in which the transmission of data is becoming a moreimportant concern. In order to achieve superior error performance athigher transmission rates, turbo block encoding is preferred. Thelatency endemic to block coding is not as significant an issue as it iswith the transmission of voice. New, third generation mobile wirelessstandards, like Universal Mobile Telecommunication Service (UMTS) andCDMA2000 require turbo encoding for data streams and convolutionalencoding for voice streams. These systems require a complex turbodecoder for data and a Viterbi decoder for voice. Furthermore, backwardcompatibility requires that second generation standards are alsosupported.

[0014] The transmission of voice and data provides conflictingrequirements of transmission rate versus latency and propagation delay.The current mode of addressing these problems is to provide separateencoding systems: turbo encoding for data streams and convolutionalencoding for voice streams. Consequently, different decoders are alsorequired, resulting in a multiplicity of hardware platforms and thusincreased costs for telecommunications operators.

SUMMARY OF THE INVENTION

[0015] The prior art's problem with decoding is overcome, in accordancewith the principles of the invention, by a single unified decoder forperforming both convolutional decoding and turbo decoding in the onearchitecture. The unified decoder architecture can support multiple datastreams and multiple voice streams simultaneously. The unified decodercan be partitioned dynamically to perform required decoding operationson varying numbers of data streams at different throughput rates. Theunified decoder also supports simultaneous decoding of voice(convolutional decoding) and data (turbo decoding) streams.Advantageously, the unified decoder can be used to decode all of thestandards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Thepreferred embodiment is modular and thus readily scalable.

[0016] The reconfigurable architecture is capable of decoding datacommunication signals transmitted according to one of the plurality ofcoding schemes. The architecture includes: a trellis processingarrangement for receiving an input signal derived from the transmittedsignals and new path metrics for determining intermediate decodedresults using path metrics; an intermediate store for receiving modifieddecoded results and for providing a decoding output; and a controller.The controller is coupled to the trellis processing arrangement and isable to configure the architecture to perform one of convolutional orturbo decoding by forming the new path metrics using generated pathmetrics output from the trellis processing arrangement, determining themodified decoded results from the intermediate decoded results, anddetermining the decoded output from a selected one of the modifieddecoded results.

[0017] In accordance with one embodiment, a telecommunications decodingdevice consists of decoding processors and at least one store arrangedin a processing loop. The device includes a control arrangement capableof reconfiguring the processing loop such that the processing loop canoperate in accordance with at least two different coding schemes.

[0018] Another embodiment is directed to a telecommunications decodingdevice, which is capable of being scaled in either one or both of thetime and space domains. In accordance with the principles of theinvention, the decoding device consists of atomic processing units, eachof which is capable of decoding input data provided according to one ofa plurality of coding schemes. The atomic processing units may bestacked together and interconnected using an hierarchical switchingstructure. The individual processing units can perform independently asseparate decoders. Alternatively, the individual processing units may becombined to form a signal high speed decoder with a predeterminedprocessor being dominant. The flexibility of the architecture allowsmultiple parallel streams of input symbols to be processedcontemporaneously or a single stream of input symbols to be processedmore quickly by combining a plurality of processing units.

[0019] Advantageously, embodiments can perform both Viterbi and Log Mapcalculations by enabling one of two processors to evaluate a trellis inaccordance with a determined coding arrangement of presented inputsymbols. The flexibility afforded by the invention allowstelecommunications operators to reduce hardware costs and responddynamically to variations in the coding of transmitted signals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] A number of preferred embodiments of the present invention willnow be described with reference to the drawings, in which:

[0021]FIG. 1 is a schematic block diagram representation of acommunication network employing multiple protocols;

[0022]FIG. 2A is a schematic block diagram representation of acommunication system employing coding;

[0023]FIG. 2B is a schematic block diagram representation of a genericViterbi decoder in a communication system employing coding;

[0024]FIG. 2C is a schematic block diagram representation of a genericturbo decoder in a communication system employing coding;

[0025]FIG. 3 is a schematic block diagram representation of a unifieddecoder;

[0026]FIG. 4 is a schematic block diagram representation of anarchitecture for a unified decoder;

[0027]FIG. 5A is a schematic block diagram representation of a butterflyprocessor of FIG. 4;

[0028]FIG. 5B is a schematic block diagram representation of anAdd-Compare-Select (ACS) unit of FIG. 4;

[0029]FIG. 6A is a representation of a 32-state trellis and itscorresponding butterfly processors and path metrics;

[0030]FIG. 6B shows the resultant path metric locations;

[0031] FIGS. 7A-7E are representations of the in-place path metricaddressing at times t=1 to t=5 respectively;

[0032]FIG. 7F is a representation of the addressing of the path metriccolumns;

[0033] FIGS. 8A-8F are representations of the in-place path metricaddressing of a reverse trellis configuration;

[0034]FIG. 9A is a schematic block diagram representation of anIntermediate Decoding Memory Processor of FIG. 4;

[0035]FIG. 9B is a schematic block diagram representation of an explodedview of FIG. 9A showing a Window Memory Subsystem, Traceback Controllerand Interleaver Controller;

[0036]FIG. 9C is a schematic block diagram representation of a TracebackController of FIG. 9B;

[0037]FIG. 9D is a schematic block diagram representation of anInterleaver of FIG. 9B;

[0038]FIG. 9E is an exploded view of an Interleaver address controllerof FIG. 9D;

[0039]FIG. 9F is a schematic block diagram representation of a WindowMemory Subsystem of FIG. 9B;

[0040]FIG. 10A is a schematic block diagram representation of aLogLikelihood processor of FIG. 4 for a single row decoder;

[0041]FIG. 10B is a schematic block diagram representation of anAdd-Compare-Select Node unit of FIG. 10A;

[0042]FIG. 10C is a schematic block diagram representation of aLogLikelihood processor of FIG. 4 for an eight row decoder;

[0043]FIG. 10D is a schematic block diagram representation of an ACSunit of FIG. 10A;

[0044]FIG. 11 is a schematic block diagram representation of a bank ofbutterfly decoding processors of FIG. 4;

[0045]FIG. 12 is a schematic block diagram representation of a ReverseAddress Processor of FIG. 4;

[0046]FIG. 13 is a schematic block diagram representation ofNormalisation Subtractors of FIG. 4;

[0047]FIG. 14 is a schematic block diagram representation of aComparator of FIG. 4;

[0048]FIG. 15 is a schematic block diagram representation of a PathMetric Memory of FIG. 4;

[0049]FIG. 16 is a schematic block diagram representation of a ForwardAddress Processor;

[0050]FIG. 17 is a schematic block diagram representation of aComparator (ACS level) of FIG. 4;

[0051]FIG. 18 is a schematic block diagram representation of an InputSymbol History of FIG. 4;

[0052]FIG. 19 is a schematic block diagram representation of aLogLikelihood Ratio Processor of FIG. 4;

[0053]FIGS. 20A and 20B illustrate use of multiple decoders to implementa single Turbo decoder;

[0054]FIG. 21 is a schematic block diagram representation of twointerconnected decoders operating together as a single decoder (16-statetrellises every cycle);

[0055]FIG. 22 is a schematic block diagram representation of fourinterconnected decoders operating together as a single decoder for evenhigher performance decoding (32-state trellises every cycle); and

[0056]FIGS. 23A and 23B are schematic block diagram representations of anon-systematic encoder.

DETAILED DESCRIPTION

[0057] The preferred embodiment provides a unified decoder architecturefor wireless communication systems. The unified decoder implements thedecoding required for convolutional encoded and turbo encoded datastreams. The unified decoder architecture can support multiple datastreams and multiple voice streams simultaneously. Furthermore, thedecoder can be dynamically partitioned, as required, to decode voicestreams for different standards. The preferred embodiment is modular andthus readily scalable.

[0058]FIG. 1 shows a wireless communication network 100. A UMTS basestation 110 contains a transmitter/receiver 112, which contains adecoder module 150 a. The transmitter/receiver 112 communicates via aswitching network 160 with another UMTS transmitter/receiver 146 locatedin a remote base station 140 and containing a decoder module 150 f. Thetransmitter/receiver 112 also communicates with a mobile handset 160 a,which contains a decoder module 150 i. The transmitter/receiver 146communicates with another mobile handset 160 f, which contains a decoderunit 150 m.

[0059] The base station 140 contains further transmitter/receivers 142and 144, containing decoder units 150 d and 150 e respectively.Transmitter/receiver 142 is configured to operate as a CDMAtransmitter/receiver and communicates via the switching network 160 withremote CDMA base station 130 containing CDMA transmitter/receiver 132and decoder unit 150 c. The transmitter/receiver 142 also communicateswith a mobile handset 160 d, containing decoder unit 150 j. Thetransmitter/receiver 132 communicates with a mobile handset 160 c,containing decoder unit 150 g.

[0060] Transmitter/receiver 144 communicates via the switching network160 with remotely located base station 120, containingtransmitter/receiver 122 and decoder unit 150 b. Thetransmitter/receiver 144 also communicates with a mobile handset 160 e,containing a decoder unit 150 k. The transmitter/receiver 122communicates with a mobile handset 160 b, containing decoder unit 150 h.

[0061] The decoder units 150 a, 150 b, 150 c, 150 d, 150 e, 150 f, 150g, 150 h, 150 i, 150 j, 150 k and 150 m located in thetransmitter/receivers 112, 122, 132, 142, 144 and 146 and mobilehandsets 160 a . . . 160 f are embodiments of the unified decoderarchitecture, which have been configured to conform to differentcellular network standards.

[0062] The unified decoder architecture of FIG. 1 offerstelecommunication companies operating multiple network standards greatbenefits in flexibility and cost reduction as the same decoder block canbe used to implement many different coding schemes in different networkcomponents.

[0063]FIG. 2A shows a typical communication system 200 in which codingis used to improve the transmission of information from a transmitter210 to a receiver 270. The transmitter 210 has an information source 205supplying an input data stream to an encoder 220, in which redundantinformation is added to the input data stream in accordance with apredefined coding algorithm so as to improve the ability to detect andcorrect errors which may occur during the transmission of information asa result of noise sources present in a communication channel 240. Theencoded input stream is then modulated 230 to impress the encoded datastream onto a waveform to be transmitted. The encoded information istransmitted over a channel 240, which has many sources of noise 280acting upon it. The channel 240 couples to a receiver 270 having ademodulator 250 complementing the modulator 230, the demodulator 250producing an output to a decoder 260, which outputs a receivedinformation signal 275.

[0064]FIG. 2B shows the communication system 200, in which the decoder260 is a generic Viterbi decoder. The input to the Viterbi decoder 260is coded information received from the channel 240. The Viterbi decoderincludes a branch metric calculator (BMC) unit 289, whose output ispresented to an add-compare-select (ACS) unit 291. A state controller290 provides inputs to the BMC unit 289, the ACS unit 291 and a pathmetric memory 292. The path metric memory 292 acts as a double bufferand interchanges information with the ACS unit 291. A borrow output 294of the ACS unit 291 is presented to a traceback memory and controller293, whose output is the received information signal 275.

[0065]FIG. 2C shows a Turbo decoding configuration of the decoder 260 ofFIG. 2A. A received symbol in a turbo decoder consists of systematicdata, representing the actual data being transmitted, and parity data,which represents the coded form of the data being transmitted. A firstinput 261, being the parity data of the received symbol, is presented toa demultiplexer 263. A first output 264 of the demultiplexer 263 ispresented to a first decoder 266. A second input 262, being thesystematic data of the received symbol, is presented to the firstdecoder 266. A recursive input 277 is also presented to the firstdecoder 266. The output 267 of the first decoder 266 is then presentedto an interleaver 268, whose output 269 is presented to a second decoder271. A second output 265 of the demultiplexer 263 is also presented tothe second decoder 271. A first output 272 of the second decoder 271 ispresented to a first deinterleaver 274, whose output is the recursiveinput 277. A second output 273 of the second decoder 271 is presented toa second deinterleaver 276. The output of the second deinterleaver 276is presented to a slicer 278, which applies a threshold to a soft outputto convert it to a hard output, being a received information signal 275.

[0066] The unified decoder architecture of the preferred embodiment isintended to replace the decoder 260 in wireless communication systemshaving both voice and data capabilities and exploits the similarity inthe computations needed for Viterbi decoding and LOG-MAP Turbo decodingso that memory and processing units are used efficiently when configuredfor either of such schemes. LogMAP is an algorithm which may be utilisedin the decoding of convolutional codes. LogMAP is also used in one halfcycle of a turbo decode iteration. Processors within the preferredembodiment are stacked together and interconnected using a hierarchicalswitching structure so that they can perform independently as separatedecoders or, alternatively, they may be combined to form a single highspeed decoder, with a predetermined processor being dominant.

[0067]FIG. 3 shows the block architecture of a unified decoder structure900 in accordance with an embodiment of the present invention. Amulti-bit input symbol 901 from an alphabet of a prior agreed codingscheme for a particular transmission is broadcast to a bank of butterflydecoding processors 920. The bank of butterfly decoding processors 920also receives as inputs the outputs of a bank of first stores 940. Acontrol unit 960 provides inputs to each of an intermediate decodingresult memory 910, the bank of butterfly decoding processors 920, thebank of first stores 940 and a bank of a second stores 950. The controlunit 960 issues appropriate control signals via the inputs to implementconvolutional or turbo coding, as desired.

[0068] The embodiment depicted in FIG. 3 is that of a single rowdecoder. When multiple decoder rows are interconnected to form a singledecoder, each of the decoder rows in the single decoder is presentedwith the same multi-bit input symbol 901. When multiple decoder rows areacting as multiple decoders, each decoder being implemented is presentedwith a separate multi-bit input symbol 901.

[0069] The bank of butterfly decoding processors 920 produces firstoutputs 962, 964, 966 and 968, which are transmitted via a bus 990 tothe bank of second stores 950. Outputs of the bank of second stores 950are presented as inputs to the bank of first stores 940. A genericembodiment of the decoder typically uses a bank of first stores 940 anda bank of second stores 950 in a double buffering mode.

[0070] The bank of butterfly decoding processors 920 produces secondoutputs 961, 963, 965 and 967, which are intermediate decoding resultspresented to the control unit 960.

[0071] The bank of butterfly decoding processors 920 and the loopfeedback connection via at least one of the stores form a loopfunctioning as a trellis processor.

[0072] The intermediate decoding result memory 910 produces a decodedoutput 999. The intermediate decoding result memory 910 may providerecursive results to the control unit 960 when computing a LogMAPalgorithm, as described later.

[0073]FIG. 4 shows the block architecture of a unified decoder 1200 inaccordance with a preferred embodiment of the present invention. Acontrol unit 1210 of the unified decoder 1200 receives a number ofinputs, including rate 1201, constraint length 1202, convolutional orturbo selector 1203, polynomials 1204, trellis direction 1205, number ofiterations 1206, block length 1207, clock 1208 and reset 1209. The rate1201 indicates how much information is used to represent a single databit present in a transmitted block. The constraint length 1202 indicateshow many previous input symbols are used to encode a presented inputinformation bit and is, thus, also an indicator of the complexity of thetrellis being processed to decode a given input symbol. The polynomials1204 are generator polynomial coefficients used in the decoding process.The number of iterations 1206 determines how many loops are executed bythe decoder 1200 when operating in turbo mode. A larger value for thenumber of iterations 2106 indicates a more accurate decoded output 1294at the cost of increased computational time.

[0074] The control unit 1210 is interconnected to an IntermediateDecoding Memory and Processor 1240, LogLikelihood Processors 1250 a and1250 b, a bank of multiplexers 1250 c, a Comparator 1247, ButterflyDecoding Processors 1260, a Reverse Address Processor 1270,Normalisation Subtractors 1278, a bank of multiplexers 1278 a, a PathMetric Store 1280, a Forward Address Processor 1290, a LogLikelihoodRatio Processor 1297 and an Input Symbol History 1298. The Control unit1210 is able to reconfigure the architecture of the unified decoder 1200via these connections to implement either a convolutional decoder or aturbo decoder, as desired.

[0075] Input symbols 1299 are presented to an Input Symbol History 1298,which functions as a double buffer to ensure that a constant data flowis maintained. The Input Symbol History 1298 also receives an InputSymbol History Bank Select 1211, an Input Symbol History Address 1219,an Input Symbol History Clock 1223 and an Input Symbol History Reset1225 from the control unit 1210. The Input Symbol History 1298 producesa first output 1291 a, which is presented to Butterfly DecodingProcessors 1260, and a second output 1291 b, which is presented toLogLikelihood Processor 1250 a.

[0076] The Butterfly Decoding Processors 1260 also receive as inputsreverse trellis path metrics 1265 from the Reverse Address Processor1270, and extrinsic information 1242 from the Intermediate DecodingMemory and Processor 1240. The control unit 1210 also provides a numberof inputs to the Butterfly Decoding Processors 1260, including aButterfly Reset 1215, Butterfly Rate 1216, Butterfly Clock 1217,Butterfly Polynomials 1218, Butterfly Constraint 1220, Butterfly Mode1221 and beta-phase enable 1235.

[0077] The Butterfly Decoding Processors 1260 produce new multiple bitpath metrics for a corresponding state in a trellis diagram, the newpath metrics being output on the 32 bit buses 1266 and 1267, which areconnected to a Comparator 1247 and a bank of multiplexers 1250 c. TheButterfly Decoding Processors 1260 also produce decision bits 1255,which are presented as inputs to the Intermediate Decoding Memory andProcessor 1240.

[0078] In a first phase of a LogMAP computation, the Butterfly DecodingProcessors 1260 compute gammas and alphas. In a second phase, theButterfly Decoding Processors 1260 calculate betas using dummy betascomputed by LogLikelihood Processor 1250 a and LogLikelihood Processor1250 b in the first phase.

[0079] Each butterfly processor within the bank of butterfly processor1260 contains two Add-Compare-Select units (shown as ACS) 320 and anintermediary Branch-Metric Calculator (BMC) 330, as depicted in FIG. 5A.The BMC 330 executes the same functions as the Branch Metric Units(BMUs) in well-known Viterbi decoders and each ACS 320 performs pathmetric calculation for trellis decoding.

[0080]FIG. 5A shows an exemplary butterfly unit of the butterflyprocessors 1260 of FIG. 4, having two Add-Compare-Select units 320 andan intermediary Branch-Metric calculator 330. Each of theAdd-Compare-Select units 320 is presented with input path metric-0 1265a and input path metric-1 1265 b. The Input Symbol 1291 a and extrinsicinformation 1242 are broadcast to each of the Branch Metric Calculators330 in the bank of butterfly processors 1260. The intermediaryBranch-Metric calculator is also presented with a butterfly rate 1216, abutterfly constraint 1220 and butterfly polynomials 1218.

[0081] Each state in a column of a trellis has a pair of branch metricsleading to it. Each of the individual branch metrics has a symbolassociated with it. Therefore, when navigating a trellis in a givendirection, one of two possible symbols is expected for a state underconsideration, depending on the previous states. The BMC 330 determinesa measure of the proximity of the received input symbol 1291 a to anexpected symbol. The BMC 330 generates an output branch metric-0 406,which is presented to a first ACS unit-0 320 and a second ACS unit-1 320on a bus being m bits wide. The BMC 330 exploits the symmetry of thetrellis and produces a second branch metric-1 402, by arithmeticallyinverting the branch metric-0 406. The branch metric-1 402 is presentedto the first ACS unit-0 320 and the second ACS unit-1 320 on a bus whichis also m bits wide. A butterfly mode 1221 is presented to each of theACS units 320 to configure them appropriately for the coding scheme inuse. The ACS units 320 and the BMC unit 330 also receive a butterflyreset 1215, a butterfly clock 1217 and a beta-phase enable 1235.

[0082] Each of the ACS units 320 generates two outputs which, for ACS 0in FIG. 5A, consist of a first output 1255 a and a second output 1267 a.The first output 1255 a is a decision bit which is the value of thecomparison borrow bit, indicating which of the upper or lower potentialpath metrics is selected. A decision bit with a value of 0 correspondsto the lower potential path metric being selected, whereas conversely avalue of 1 corresponds to the upper potential path metric beingselected. The second output 1267 a is a new multiple bit path metric fora corresponding state in a trellis diagram. ACS 1 produces correspondingoutputs 1255 b and 1267 b.

[0083]FIG. 5B shows an architecture of an ACS unit-0 320 of FIG. 5A. Twopairs of inputs 402 and 1265 b, and 406 and 1265 a are presented torespective Adders 410 and 412. The first pair of inputs consists of thebranch metric-1 402 and path metric-1 1265 b, whereas the second pair ofinputs consists of branch metric-0 406 and path metric-0 1265 a. Theconstituent elements of each of the input pairs are added in respectiveadders 410 and 412, the corresponding outputs 411 and 413 of the adders410 and 412 being presented to a Full Subtractor 414. The outputs 411and 413 are also presented to a first two-to-one multiplexer 420. Aborrow output 1255 a of the Full Subtractor 414 is fed to the firstmultiplexer 420 to compute a maximum MAX of the input values. The borrowbit 1255 a is also presented as an output of the ACS unit 320, with avalue of 0 indicating that the lower path metric has been chosen and avalue of 1 indicating that the upper path metric has been selected. Asecond output 415 of the Full Subtractor 414, representing thedifference of the two adder results 411 and 413, is presented to aLog-sum correction table 440, which adjusts the result of the new pathmetric, when the output of the Full Subtractor 414 is small, to producea more accurate result in the Log domain for LogMAP decoding. An output441 of the Log-sum correction table 440 is presented to an Adder 460. Anoutput 421 of the first multiplexer 420 is presented to the Adder 460and to a second two-to-one multiplexer 450. A result 461 from the Adder460 is then presented as a second input to the second multiplexer 450. Acontrol signal, being butterfly mode 1221, is also presented as an inputto the second multiplexer 450 and is used to determine whether theViterbi or LogMAP coding scheme is being implemented. The secondmultiplexer 450 forms an output 451, which feeds an Accumulate Register470 and a further multiplexer 480. The Accumulate Register 470 receivesa butterfly reset 1215 and produces an output 472 to the multiplexer480. The multiplexer 480 receives a beta-phase enable 1235 as a selectsignal that selects the output 451 when inactive and the output 472 fromthe Accumulate register 470 when active. The selected output of themultiplexer 480 is the output path metric 1267 a of the ACS unit 320.

[0084] The bank of multiplexers 1250 c receives a select signal 1258from the control unit 1210, which is used to select either the butterflypath metrics 1266 and 1267 output from the Butterfly Processors 1260 orthe path metrics produced by the LogLikelihood Processor-0 1250 a andLogLikelihood Processor-1 1250 b. During a Viterbi calculation, thebutterfly path metrics 1266 and 1267 are selected. In the first phase ofa LogMAP computation, butterfly path metrics 1266 and 1267 are chosenwhilst the Butterfly Decoding Processors 1260 compute gammas and alphas.Contemporaneously, LogLikelihood Processor 1250 a calculates dummybetas. At the end of the first phase, the path metrics produced by theLogLikelihood Processor-0 1250 a are selected by the bank ofmultiplexers 1250 c to be broadcast to enable the calculation of betasin the second phase of the LogMAP computation.

[0085] The bank of multiplexers 1250 c outputs new path metrics on LowerPath Metric Bus 1295 and Upper Path Metric Bus 1296. The buses 1295 and1296 are connected to LogLikelihood processors 1250 a and 1250 b, a bankof multiplexers 1278 a and a Forward Address Processor 1290.

[0086] The Forward Address Processor 1290 receives a Forward TrellisSelect 1232, a Forward Trellis Hold 1234, a Forward Trellis TransparentBit 1236 and a Path Metric Input MUX Select 1238 from the control unit1210, which are used to configure the Forward Address Processor 1290 inaccordance with whether the unified decoder 1200 is being used tonavigate a trellis in the forward or reverse direction.

[0087] The Forward Address Processor 1290 orders the new path metricsreceived on buses 1295 and 1296 such that an apparently sequential listof path metrics is presented to the butterfly processor 1260 forcomputation of the next column of the trellis, when the trellis is beingnavigated in the forward direction. When a trellis is being navigated inthe reverse direction, the Forward Address Processor 1290 actstransparently.

[0088] The Path Metric Store 1280 receives addressing information ADDR01228 a and ADDR1 1228 b, Path Metric Reset 1230 and Path MetricRead/Write Clock 1231 from the control unit 1210, in addition to forwardtrellis path metrics 1285, which are output from the Forward AddressProcessor 1290. The Path Metric Store 1280 outputs stored path metrics1276 to a bank of multiplexers 1278 a and to LogLikelihood Processors1250 a and 1250 b.

[0089] The bank of multiplexers 1278 a is used as an interconnect pointfor multiple decoder row configurations, and receives stored pathmetrics 1276, a control signal 1278 b from the control unit 1210, andnew path metrics on buses 1295 and 1296. The bank of multiplexers 1278 aallows the initialisation of the beta computation during LogMAPcalculation and produces an output 1277 to Normalisation Subtractors1278.

[0090] A comparator 1247 receives the butterfly path metrics output onbuses 1266 and 1267 from the Butterfly Decoding Processors 1260 anddetermines a maximum new path metric. This maximum new path metric isthen compared with a stored maximum path metric and the greater of thetwo values is presented as normalising output 1246, which is sent to theNormalisation Subtractors 1278 and the Intermediate Decoding Memory andProcessor 1240.

[0091] The Normalisation Subtractors 1278 receive the output 1277 fromthe bank of multiplexers 1278 a and subtract the Normalising Output 1246to ensure that the path metrics are contained within the dynamic rangeof the architecture. The normalised path metrics 1275 are output andpresented to a Reverse Address Processor 1270 and LogLikelihoodProcessors 1250 a and 1250 b. The Reverse Address Processor 1270 alsoreceives as inputs LogLikelihood Enable 1214, LogLikelihood 0 Enable12030 and LogLikelihood 1 Enable 12031, Reverse Trellis Select 1222, aReverse Trellis Hold 1224 and a Reverse Trellis Transparent Bit 1226from the control unit 1210. The inputs from the control unit 1210 areused to configure the Reverse Address Processor 1270 appropriately,depending on whether the decoder 1200 is traversing a trellis in theforward or reverse direction. The output of the Reverse AddressProcessor 1270 is presented as reverse trellis path metrics 1265 to theButterfly Decoding Processors 1260.

[0092] The Reverse Address Processor 1270 orders the normalised pathmetrics such that a desired sequence of path metrics is presented to thebutterfly processor 1260 for computation of the next column of thetrellis, when the trellis is being navigated in the reverse direction.When the trellis is being navigated in the forward direction, theReverse Address Processor 1270 acts transparently.

[0093] The LogLikelihood Processor 1250 a receives a LogLikelihood Mode1214 a, reverse trellis hold 1224 a, reverse trellis transparent bit1226 a, a LogLikelihood rate 1248 a, a LogLikelihood constraint 1249 a,a LogLikelihood clock 1251 a, a LogLikelihood reset 1252 a,LogLikelihood polynomials 1253 a, LogLikelihood 0 Enable ¹²⁰³ a ₀,LogLikelihood Enable 1203 a ₁, reverse trellis select 1222 a, and selectsignal 1258 a from the control unit 1210. The LogLikelihood Processor1250 a also receives as inputs the normalised path metrics 1275, theoutput 1291 b from the Input Symbol History 1298, stored path metrics1276, new path metrics on buses 1296 and 1295 and interleaver extrinsicinformation 1256. The LogLikelihood processor 1250 a produces a firstoutput 1245 a, which is presented to a LogLikelihood Ratio Processor1297. The LogLikelihood processor 1250 a also presents inputs 1266′ and1267′ to the bank of multiplexers 1250 c.

[0094] A second LogLikelihood processor 1250 b receives correspondinginputs 1214 b, 1224 b, 1226 b, 1248 b, 1249 b, 1251 b, 1252 b, 1253 b,1203 b ₀, 1203 b ₁, 1222 b and 1258 b from the control unit 1210. TheLogLikelihood Processor 1250 b also receives as inputs the normalisedpath metrics 1275, stored path metrics 1276, interleaver extrinsicinformation 1256 and the new path metrics on buses 1296 and 1295. TheLogLikelihood processor 1250 b produces an output 1245 b, which ispresented to the LogLikelihood Ratio Processor 1297.

[0095] The LogLikelihood Processor 1250 a is used to compute dummy betasin the first phase of a LogMAP calculation. In the second phase of theLogMAP calculation, LogLikelihood Processors 1250 a and 1250 b are usedin conjunction with the Butterfly Decoding Processors 1260 to create aLogLikelihood result for a “1” and a “0”, respectively.

[0096] The Intermediate Decoding Memory and Processor 1240 acts as abuffer for producing output during a Viterbi computation. During aLogMAP computation, the Intermediate Decoding Memory and Processor 1240acts as an extended store for the path metric store 1280. TheIntermediate Decoding Memory and Processor 1240 receives an IntermediateDecoding Mode 1212, an Intermediate Decoding Direction 1237, a SpreadingInput 1243, read/write clock 1257, a reset 1259 and a clocking signal1254 from the control unit 1210. The Intermediate Decoding Memory andProcessor 1240 also receives the Normalising Output 1246 and DecisionBits 1255. The Intermediate Decoding Memory and Processor 1240 producesextrinsic information 1242 and Traceback processor output 1567 to theLogLikelihood Ratio Processor 1297, and receives an input 1293 from theLogLikelihood Ratio Processor 1297. The Intermediate Decoding Memory andProcessor 1240 also produces interleaver extrinsic information 1256 toLogLikelihood Processors 1250 a and 1250 b.

[0097] The LogLikelihood Ratio Processor 1297 receives a Hard or SoftOutput Select 1213 and Spreading Input 1243 from the control unit 1210in addition to the outputs 1245 a and 1245 b from the LogLikelihoodProcessors 1250 a and 1250 b. The LogLikelihood Ratio Processor 1297also receives as inputs the extrinsic information 1242 of theIntermediate Decoding Memory and Processor 1240 and Scramble AddressData 1286. The LogLikelihood Ratio Processor 1297 then produces aDecoded Output 1294 and an output 1293 to the Intermediate DecodingMemory and Processor 1240.

[0098] The outputs 1245 a and 1245 b represent the probability of thedecoded output being a “1” or a “0”, respectively. The LogLikelihoodRatio Processor 1297 performs a subtraction of the outputs 1245 a and1245 b in the log domain, which is equivalent to performing a divisionin the natural number domain. The result of the subtraction provides theDecoded Output 1294. The LogLikelihood Ratio Processor 1297 alsosubtracts the outputs 1245 a and 1245 b and the extrinsic information1242 to produce the output 1293, which represents new extrinsicinformation.

[0099] A code of maximum constraint length k produces a trellis diagramwith 2^(k−1) states. FIG. 6A shows a 32-state raw trellis diagram 1000,corresponding to a code having a maximum constraint length of 6. Each ofthe 32 states 1002 at time S₁ has two possible branch metrics mapping toone of 32 states 1004 at time S_(t+1). For example state 0 1003 at timeS_(t) has branch metrics 1006 and 1008 leading to state 0 1009 and state16 1007 at time S_(t+1).

[0100] The 32-state raw trellis diagram 1000 may be represented by 16corresponding butterfly connections 1010 of the same trellis. It can beseen that pairs of states in one column 1012 of the trellis map tocorresponding pairs of states in another column 1014 of the trellis. Thetrellis states 1014 at time S_(t+1) represent resultant path metrics.Each of the butterfly connections 1010 may be processed by a singlebutterfly processor 1260. In accordance with a preferred embodiment ofthe invention, as shown in FIG. 4, four butterfly processors 1260 areprovided. This allows 8 resultant path metric locations to be calculatedin each clock cycle.

[0101]FIG. 6B shows the resultant path metric locations 1014 for a32-state trellis diagram. The 32 resultant path metric locations havebeen ordered into four columns 1022, 1024, 1026 and 1028, each of whichcontains eight resultant path metric locations produced by fourbutterfly processors.

[0102] A trellis operation incorporates several sub-trellis operations,each of which corresponds to a single clock cycle. FIGS. 7A, 7B, 7C, 7Dand 7E show the process by which a preferred embodiment of the inventionimplements in-place path metric addressing. FIG. 7A shows time t=1,corresponding to the first sub-trellis operation, in which eight newpath metrics 1112 are presented as inputs. New path metrics 1112representing 0, 1, 2 and 3 are written into a first column of memory1102, corresponding to upper memory blocks B0 of Path Metric Store 1280,whilst path metrics 16, 17, 18 and 19 are written into four holdingregisters 1114. Path metrics 16, 17, 18 and 19 are held for a clockcycle before being written to memory, as the memory locations to whichthey will be written will not become available until the next clockcycle when the new path metrics for trellis states 8 to 15 have beencalculated.

[0103] In the next clock cycle t=2, shown in FIG. 7B, a further eightnew path metrics 1122 are presented as inputs. The path metrics 1122corresponding to new path metric locations 4, 5, 6 and 7 are writteninto a first column of memory 1104, corresponding to lower memory blocksB1 of Path Metric Store 1280. The contents of the holding registers 1114are written into a second column of memory 1102, corresponding to PathMetric Store 1280 B0 and the new path metrics corresponding to pathmetric locations 20, 21, 22 and 23 are written in as the new contents ofthe holding registers 1114.

[0104] In the third clock cycle shown in FIG. 7C, a further group of newpath metrics 1134 is presented. The new path metrics corresponding tostates 8, 9, 10 and 11 are written into a third column of memory 1102,corresponding to Path Metric Store 1280 BO and the contents of theholding registers 1114, being states 20, 21, 22 and 23, are written intoa second column of a memory 1104, corresponding to Path Metric Store1280 B1. The four new path metrics corresponding to states 24, 25, 26and 27 are written into the holding registers 1114.

[0105]FIG. 7D shows the fourth clock cycle, during which the final eightnew path metrics 1144 are presented. The new path metrics correspondingto states 12, 13, 14 and 15 are written to a third column of memory1104, corresponding to Path Metric Store 1280 B1, the contents of theholding register corresponding to states 24, 25, 26 and 27 are writtento a fourth column of memory 1102, corresponding to Path Metric Store1280 B0, and the new path metrics corresponding to states 28, 29, 30 and31 are written to holding registers 1114.

[0106] An additional clock cycle corresponding to t=5, as shown in FIG.7E, is required to write the contents of the holding registers 1114 intoa fourth column of memory 1104, corresponding to Path Metric Store 1280B1.

[0107]FIG. 7F shows a representation of the addressing of the pathmetric columns for a 32-state trellis in accordance with a preferredembodiment of the present invention. The addressing sequence of the pathmetric columns 1150 corresponds to the read/write addresses of the pathmetric columns. Each row of the table 1160 corresponds to a differentcolumn of a trellis diagram, representing Symbol time n (S_(n)), Symboltime n+1 (S_(n+1)) and Symbol time n+2 (S_(n+2)). It is evident that themovement of the addresses of the path metric columns is periodic.

[0108] FIGS. 7A-E have shown the progression from S_(n) to S_(n+1). Thenext clock cycle, t=6, will begin the transition from S_(n+1) to S_(n+2)and columns 0, 2, 1, 3 will be executed in order to present a sequentiallist of states to the ACS units.

[0109]FIGS. 8A, 8B, 8C, 8D, 8E and 8F show the process by which apreferred embodiment of the invention implements in-place path metricaddressing during navigation of a reverse trellis. FIG. 8A depicts thenotation that will be followed in FIGS. 8B-F. FIG. 8B shows time t=1,corresponding to the first sub-trellis operation. The path metricsresident in the first column of memory A, C_(0A), have been shifted to ahold register 3010. In FIG. 8C, time t=2, the first column of memory B,C_(0B), is moved to the hold register 3010 and a function of C_(0A) andC_(2A) form resultant path metrics C_(0A)′ and C_(0B)′, which arewritten into the first column of memories A and B respectively. In FIG.8D, the second column of memory A C_(1A) is deposited in the holdregister 3010. A function of the previous contents of the hold registerC_(0B) and C_(2B) form new path metrics C_(1A)′ and C_(1B)′ which arewritten back into the third column of A and B respectively.

[0110]FIG. 8E shows time t=4 in which C_(1B) is written to the holdregister 3010. A function of C_(1A) and C_(3A) produces new path metricsC_(2A)′ and C_(2B)′, which are written into the second columns ofmemories A and B respectively. FIG. 8F shows the reverse sub-trellisoperation corresponding to time t=5 in which a function of C_(1B) andC_(3B) forms resultant path metrics C_(3A)′ and C_(3B)′ which arewritten into fourth columns of memories A and B respectively. In thecalculations of the reverse trellis, path metrics are presented to fourbutterfly processors in a scrambled manner and the in-place path metricaddressing described in FIGS. 8B to 8F ensures that the resultant pathmetrics are presented in a sequential manner.

[0111]FIG. 9A shows a high level schematic block diagram representationof an embodiment of the Intermediate Decoding Memory and Processor 1240,which performs traceback and interleaver functions in respectivedecoding schemes. The Intermediate Decoding Memory and Processor 1240receives as inputs decision bits 1255, normalising output 1246,spreading input 1243, intermediate decoding direction 1237, intermediatedecoding mode 1212, a clocking signal 1254, a read/write clock 1257, areset signal 1259 and the output 1293 from the LogLikelihood processor1297. The Intermediate Decoding Memory and Processor 1240 producesoutputs including extrinsic information 1242, interleaver extrinsicinformation 1256 and Traceback processor output 1567.

[0112]FIG. 9B shows an exploded view of the Intermediate Decoding Memoryand Processor 1240. A Traceback Address Controller 1510 receives asinputs Decision Bits 1255, the Intermediate Decoding Direction 1237,Norrnalising Output 1246, the clocking signal 1254, reset signal 1259,read/write clock 1257 and the Intermediate Decoding Mode 1212, which isinverted. The Traceback Address Controller 1510 produces an output 1567.

[0113] The Traceback Address Controller 1510 writes Decision Bits 1255to a Window Memory Subsystem 1520 every clock cycle. During traceback,the Traceback Address Controller 1510 examines a trellis section todetermine a biggest value to be used as a starting point. It is to benoted that it is not necessary to store the complete value for eachstate as a new traceback byte address can be generated using one of theDecision Bits 1255.

[0114] An Interleaver Controller 1520 also receives a clocking signal1254, reset signal 1259, read/write clock 1257 and Intermediate DecodingMode 1212. In addition, the Interleaver Controller 1520 receives theoutput 1293 from the LogLikelihood Ratio Processor 1297, the SpreadingInput 1243 and the Intermediate Decoding Direction 1237. The InterleaverController 1520 produces extrinsic information 1242 and 1256. Theextrinsic data 1242 is used as a recursive input to the ButterflyProcessors 1260 when the decoder 1200 operates as a Turbo decoder.

[0115] The Interleaver Controller 1520 produces extrinsic information1242 and 1256 at the beginning of every clock cycle. At the end of everyclock cycle, the Interleaver Controller 1520 receives new extrinsicinformation in the form of the output 1293 from the LogLikelihood RatioProcessor 1297 and writes it into memory.

[0116] The Traceback Address Controller 1510 and Interleaver Controller1520 are interconnected and supply a joint read/write signal 1515 to aWindow Memory Subsystem 1530. The Traceback Address Controller 1510,Interleaver Controller 1520 and Window Memory Subsystem 1530 are furtherinterconnected by a bi-directional data bus 1526 and an address bus1525. The Interleaver Controller 1520 has a second address bus 1535connected to the Window Memory Subsystem 1530 and the Window MemorySubsystem 1530 produces an output on a second data bus 1536 to theInterleaver Controller 1520.

[0117]FIG. 9C shows the Traceback Processor 1510. The decision bits 1255are presented to a first multiplexer 1550. The output of the multiplexer1550 is presented to a decisions register 1555. The output of thedecisions register 1555 is data 1526, which is presented as an output ofthe Traceback Processor 1510 and is also fed back as a recursive inputof the first multiplexer 1550 and as an input to a bit select 1558.

[0118] The Intermediate Decoding Direction 1237 is presented as an inputto an address translation unit 1560. The address translation unit 1560also receives a read/write clock 1257 and produces an output address1525 and a read/write signal 1515. The read/write clock 1257 is alsopresented as the select of the first multiplexer 1550.

[0119] A normalising output 1246 is presented as an input to a stateregister 1562. The output of the state register 1562 is presented as aninput to the address translation unit 1560, as well as being an input toa previous state unit 1564. The previous state unit 1564 presents twoinputs to a second multiplexer 1566, whose output is the TracebackProcessor Output 1567.

[0120] The output of the bit select 1558 is presented as an input to afirst AND gate 1568. The output of the AND gate 1568 is presented as aninput to the state register 1562. The output of the bit select 1558 isalso presented to a second AND gate 1569, whose output is also presentedto the state register 1562.

[0121] The Intermediate Decoding Direction 1237 is presented as thesecond input to the first AND gate 1568 and as the select input of themultiplexer 1566. The decode unit output 1502 is also presented, via aNOT gate 1570, to the second AND gate 1569.

[0122]FIG. 9D shows the interleaver controller of 1520 of FIG. 9B. TheIntermediate decoding mode 1212 is presented to an AND gate 1580, whoseoutput is presented to two tri-state buffers 1582 and 1583. The otherinput to the AND gate 1580 is the inverted form of the spreading input1243. The tri-state buffer 1582 also receives as a input a read/writeclock 1257. The second tri-state buffer 1583 receives the output 1293from the LogLikelihood ratio processor 1297 as its second input. Theoutput 1293 from the LogLikelihood Ratio Processor 1297 is alsopresented as inputs to two logic blocks 1584 and 1586. The spreadinginput 1243 is presented to each of the logic blocks 1584 and 1586, as isthe reset signal 1259, and the clock signal 1254. The Interleaver 1520receives data bus 1526 as an input and presents a corresponding outputbeing extrinsic information 1242. A second data bus 1536 is output asinterleaver extrinsic information 1256. The data bus 1526 isbi-directional, and the output of the Interleaver 1520 to the data bus1526 is the output of the tri-state buffer 1583.

[0123] The first logic block 1584 receives the intermediate decodingmode 1212 and the intermediate decoding direction 1237 and produces anaddress 1525. The second logic block 1586 also receives the intermediatedecoding mode 1212 and intermediate decoding direction 1237 and producesaddress 1535. Each of the logic blocks 1584 and 1586 also receive aninput beta_d, which is a low or high power signal.

[0124]FIG. 9E shows an exploded view of the logic block 1584 of FIG. 9D.The logic block 1586 of FIG. 9D has the same configuration. A windowcount 1590 receives as inputs a reset 1259, a clock 1254 and an enable1212. It also receives as an input the output of a first adder 1592. Thewindow count 1590 produces an output which is presented to adders 1592and 1593. The first adder 1592 receives as a second input the constant1599 and presents its output to the window count 1590. The bit count1591 receives as inputs the reset 1259, the clock 1254, the enable 1212and the output of a third adder 1594. The bit count 1591 produces anoutput which is presented to two adders 1593 and 1594. Beta d ispresented to an element 1595, which adds 1 and if beta_d is active, itnegates the value and presents a result as a second input to the thirdadder 1594. The output of the adder 1594 is presented as a recursiveinput to the bit count 1591.

[0125] The output of the second adder 1593 is presented as an input to amultiplexer 1596 and to a scramble 1597. The multiplexer 1596 receives aselect signal indicating if the architecture is operating as a first orsecond decoder, and a second input being the output of the scramble1597. The output of the multiplexer 1596 is the address 1525. Thescramble 1597 receives the Spreading Input 1243 as an enabling signaland the output 1293 from the LogLikelihood Ratio Processor 1297 as data.The scramble 1597 could be memory or logic function as is well known inthe art and is used to implement scrambling of addresses between a firstand second decoder when undertaking Turbo decoder calculations.

[0126]FIG. 9F shows a schematic block diagram representation of thewindow memory sub system 1530 of FIG. 9A. A read/write clock 1515,address buses 1525 and 1535, and data buses 1526 and 1536 are presentedto a window address decoder 1530 a and window memories 1530 b . . . 1530d.

[0127]FIG. 10A shows the LogLikelihood Processor 1250 a of FIG. 4. Abank of four butterfly units 1410 is provided and its constituent ACSunits 1412 a . . . 1412 h are presented with pairs of reverse trellispath metrics 1415 a . . . h from a Reverse Address Processor 1270 b andstored path metrics 1276 from the Path Metric Store 1280. The storedpath metrics 1276 represent alphas in the LogMAP calculation. Each ofthe ACS units 1412 a . . . h is also presented with a LogLikelihood Mode1214 a, a LogLikelihood Clock 1251 a and a LogLikelihood Reset 1252 a.BMC units 1414 a . . . 1414 d are each provided with a number of inputs,including the LogLikelihood Rate 1248 a, the LogLikelihood Constraint1249 a, the LogLikelihood Polynomials 1253 a, interleaver extrinsicinformation 1256 and the Input Symbol History 1291 b. The ACS units 1412a . . . h produce first outputs 1413 a . . . 1413 h, which are presentedin sequential pairs to the ACS node units 1420 a . . . 1420 d. The ACSunits 1412 a . . . h produce second outputs 480 a . . . h, each of whichis presented to a corresponding normalising subtractor 1470 a . . . 1470h. The normalising subtractors 1470 a . . . 1470 h produce outputs 1266′and 1267′, which are fed recursively via multiplexers, as explainedbelow, to the Reverse Address Processor 1270 b and used to ensure thatthe path metrics remain within the dynamic range of the architecture.

[0128] Each of a first bank of multiplexers 1417 a . . . h receives acorresponding normalised path metric 1275 a . . . h from the NormalisingProcessor 1278 and a select signal 1258 from the control unit 1210.Multiplexers 1417 a . . . d also receive corresponding path metrics 1296a . . . d, and multiplexers 1417 e . . . h receive corresponding pathmetrics 1295 a . . . d. The path metrics 1295 a . . . d and 1296 a . . .d represent betas in the LogMAP calculation. The select signal 1258 isused to determine whether the normalised path metrics 1275 a . . . h orthe path metrics 1295 a . . . d and 1296 a . . . d will be output.

[0129] Each of a second bank of multiplexers 1416 a . . . h receivesLogLikelihood Mode 1214 a as a select signal and a corresponding outputfrom the first bank of multiplexers 1417 a . . . h. Multiplexers 1416 a. . . d receive a third input, being the output 1266′ of the normalisingsubtractors 1470 a . . . d and multiplexers 1416 e . . . h receive theoutput 1267′ from the normalising subtractors 1470 e . . . h. Theoutputs from the multiplexers 1416 a . . . h are presented as inputs tothe Reverse Address Processor 1270 b.

[0130] The Reverse Address Processor 1270 b also receives aLogLikelihood Mode 1214 a, Turbo enable for LogLikelihood 0 Enable 1203a ₀, Turbo enable for LogLikelihood 1 1203 a ₁, reverse trellis selector1222 a, reverse trellis transparent bit 1226 a and the reverse trellishold 1224 a. The beta outputs 1266′ and 1267′ of the LogLikelihoodProcessor 1250 a represent the final dummy beta values used for thestart of the beta processing phase, when the decoder 1200 is operatingin LogMAP/turbo mode.

[0131] The outputs of the ACS node units 1420 a and 1420 b are presentedto an ACS node unit 1430 a and the outputs of the ACS node units 1420 cand 1420 d are presented to an ACS node unit 1430 b. The outputs of theACS node units 1430 a, 1430 b are presented as inputs to a further ACSnode unit 1440 a, whose output is presented to a multi-row comparatortree, which spans the decoder when operated in a multi-row configurationso as to capture the maximum path metric being calculated for the stateof the trellis being investigated. An output from the multi-rowcomparator tree is presented to a subtractor 1450 and a register 1460.The subtractor 1450 also presents a recursive input to the register1460. The register output 1245 a is fed to the subtractor 1450 and toeach one of the normalising subtractors 1470 a . . . 1470 h, in additionto being an output of the LogLikelihood Processor 1250 a.

[0132]FIG. 10B shows one arrangement of the ACS node unit 1420 a of FIG.10A. The outputs 1413 a and 1413 b from the ACS leaf units are presentedas inputs to a comparator 1474 and a multiplexer 1476. A borrow outputof the comparator 1474 is fed as a select signal of the multiplexer1476. A difference output of the comparator 1474 is presented as aninput to a log sum correction table 1478. The output of the log sumcorrection table 1478 is presented to an adder 1480, whose second inputis the output of the multiplexer 1476. The adder 1480 computes andoutputs the sum 1425 a of its two inputs, the sum 1425 a representingthe maximum of the two inputs 1413 a and 1413 b, with a log-sumcorrection.

[0133]FIG. 10C shows a configuration of a LogLikelihood processor 1250 aof FIG. 4 for an eight row decoder embodiment. The LogLikelihoodprocessors 1250 a′ in each of the rows are interconnected via a bank ofmultiplexers 1490. Each multiplexer 1490 presents a single input to aLogLikelihood processor 1250 a′ in its corresponding decoder row. Pairsof LogLikelihood processors 1250 a′ present their outputs as inputs toACS node units 1420 a′, 1420 b′, 1420 c′ and 1420 d′. The outputs of theLogLikelihood processors 1250 a′ are also presented as recursive inputsto the bank of multiplexers 1490. The ACS nodes units 1420 a′, 1420 b′,1420 c′ and 1420 d′ are paired and present their outputs as inputs tofurther ACS nodes units 1430 a′ and 1430 b′. The outputs of the ACS nodeunits 1420 a′, 1420 b′, 1420 c′ and 1420 d′ are also presented asrecursive inputs to the bank of multiplexers 1490. The ACS node units1430 a′ present their outputs to a final ACS node unit 1440′ and asrecursive inputs to the bank of multiplexers 1490. The output of thefinal ACS node unit 1440′ is presented as a final recursive input to thebank of multiplexers 1490. Each multiplexer 1490 is presented with aselect signal.

[0134]FIG. 10D shows one useful architecture of an ACS unit 1412 a ofFIG. 10A. A first pair of inputs, branch metric 1 402′ and branch metric0 406′, are presented to a multiplexer 408, which produces an output402″. A second pair of inputs, path metric 1276 a and path metric 1 1415b are presented to a multiplexer 409, which produces an output 403′.Each of the multiplexers 408 and 409 receives LogLikelihood Mode 1214 aas a select signal. When the LogLikelihood Mode 1214 a is inactive,branch metric 1 402′ is selected by multiplexer 408 and path metric 11415 b is selected by multiplexer 409. Conversely, when LogLikelihoodMode 1214 a is active, branch metric 0 406′ is selected by multiplexer408 and path metric 1276 a, representing an alpha value, is selected by409.

[0135] The outputs 402″ and 403′ of the multiplexers 408 and 409 arepresented to an adder 410′. The sum 411′ is output from the adder 410′and presented to a multiplexer 416′ and a multiplexer 417′. Themultiplexer 417′ receives branch metric 0 406′ as a second input andLogLikelihood Mode 1214 a as a select signal. The output 418′ of themultiplexer 417′ is presented to an adder 412′. The adder 412′ receivespath metric 0 1415 a as a second input. The adder 412′ produces a sum413′, which represents the sum of alphas, betas and gammas. The sum 413′is presented to a Full Subtractor 414′ and a multiplexer 420′. Themultiplexer 416′ receives a hardwired input 407′ corresponding to theminimum 2s complement number able to be represented and a LogLikelihoodMode 1214 a as a select signal. The Full Subtractor 414′ also receivesthe output 408′ of the multiplexer 416′ as a second input and produces aborrow 361′ and a difference 415′.

[0136] The output 408′ of the multiplexer 416′ is presented as a firstinput to a multiplexer 420′. The multiplexer 420′ receives the sum 413′of the adder 412′ as a second input. The borrow output 361′ of the FullSubtractor 414′ is fed to the multiplexer 420′ to compute a maximum MAXof the input values. A second output 415′ of the Full Subtractor 414′,representing the difference of the multiplexer output 408′ and the sum413′, is presented to a Log-sum correction table 440′, which tweaks theresult of the new path metric, when the output of the Full Subtractor414′ is small, to produce a more accurate result in the Log domain forLogMAP decoding. An output 441′ of the Log-sum correction table 440′ ispresented to an Adder 460′. An output 421′ of the multiplexer 420′ isalso presented to the Adder 460′. A result 490′ from the Adder 460′ isthen presented as an input to an accumulate register 470′. Theaccumulate register 470′ accumulates values for dummy beta LogMAPcalculations. The output 480 a of the accumulate register is presentedas an input to a further multiplexer 475′ and as an output of the ACSunit 1412 a to be used in dummy beta computation. The multiplexer 475′receives the sum 490′ as a second input and LogLikelihood Mode 1214 a asa select signal. The output 1413 a of the multiplexer 475′ is the secondoutput of the ACS unit 1412 a.

[0137]FIG. 11 shows Butterfly Decoding Processors 1260 of FIG. 4 inaccordance with a preferred embodiment. Each of the component ACS unitsACS0 . . . ACS7 is presented with a number of inputs, including abutterfly mode 1221, a butterfly reset 1215, a butterfly clock 1217 anda beta-phase enable 1235. Each of the component BMC units BMC0 . . .BMC3 is presented with a butterfly rate 1216, a butterfly constraint1220 and butterfly polynomials 1218. The reverse trellis path metrics1265 fan out to present inputs 1265 a . . . 1265 h to the ACS units ACS0. . . ACS7, such that each ACS unit receives two reverse trellis pathmetrics. Reverse trellis path metrics 1265 a and 1265 b are presented toeach of the ACS units ACS0 and ACS1, reverse trellis path metrics 1265 cand 1265 d are presented to each of the ACS units ACS2 and ACS3, reversetrellis path metrics 1265 e and 1265 f are presented to each of the ACSunits ACS4 and ACS5, and reverse trellis path metrics 1265 g and 1265 hare presented to each of the ACS units ACS6 and ACS7. The BMC units BMC0. . . BMC3 also receive as inputs extrinsic information 1242 and inputsymbol history input symbol 1291 a.

[0138] The Butterfly Decoding Processors 1260 are preferably formed byeight ACS units and four BMCs, configured as four butterfly processors:

[0139] (i)ACS0, BMC0, ACS1;

[0140] (ii)ACS2, BMC1, ACS3;

[0141] (iii)ACS4, BMC2, ACS5; and

[0142] (iv) ACS6, BMC3, ACS7.

[0143] The unified decoder architecture takes advantage of the fact thateach state in a trellis diagram may only be impacted upon by two otherstates. A code with a minimum constraint length of k gives rise to atrellis diagram having 2^(k−1) states. A butterfly processor having twoACS units and an intermediary BMC unit is capable of processing twostates in a trellis state diagram. Therefore, in order to process a codewith constraint length 4 in one clock cycle, a total of eight ACS unitsare required. More states may be handled by processing over a greaternumber of clock cycles, or by having more butterfly processors.

[0144] The ACS units ACS0 . . . ACS7 produce corresponding outputs 1255a . . . h, which are aggregated to form decision bits 1255. New pathmetrics computed by ACS units ACS0 . . . ACS3 are presented as outputs1267 a . . . d and sent on upper new path metric bus 1267. The new pathmetrics 1266 a . . . d calculated by ACS units ACS4 . . . 7 arepresented to the lower new path metric bus 1266.

[0145]FIG. 12 shows the Reverse Address Processor 1270 of FIG. 4. TheReverse Address Processor 1270 provides facilities for delaying andordering path metrics to produce a desired pattern of path metrics. TheReverse Address Processor 1270 is also capable of acting transparentlywhen the decoder 1200 is operating in forward trellis mode such thatinput path metrics are presented as outputs without alteration. TheReverse Address Processor 1270 receives as inputs: a reverse trellisselector 1222, a reverse trellis hold 1224, a reverse trellistransparent bit 1226, a LogLikelihood Mode 1214, a LogLikelihood 0Enable 12030, a LogLikelihood I Enable 12031, and the normalised pathmetrics 1275. The normalised path metrics 1275 fan out to present pairsof inputs 1275 a and 1275 e, 1275 b and 1275 f, 1275 c and 1275 g, and1275 d and 1275 h to a first bank of corresponding multiplexers 1910 a3, 1910 b 3, 1910 c 3 and 1910 d 3, and a second bank of correspondingmultiplexers 1915 a . . . 1915 d.

[0146] The reverse trellis selector 1222 is presented to each of thefirst bank of XOR gates 1920 a . . . d. The XOR gates 1920 a and 1920 creceive LogLikelihood 0 Enable 1203 ₀ and XOR gates 1920 b and 1920 dreceive LogLikelihood 1 Enable 1203 ₁. Each XOR gate 1920 a . . . dproduces an output which is presented to a corresponding XOR gate in asecond bank of XOR gates 1925 a . . . d and to a corresponding one ofthe multiplexers 1910 a 3 . . . 1910 d 3. Each of the second bank of XORgates 1925 a . . . d receives LogLikelihood Enable 1214 as a secondinput and produces an output to a corresponding multiplexer in thesecond bank of multiplexers 1915 a . . . d. As mentioned above, eachmultiplexer 1915 a . . . d receives a pair of normalised path metricsThe outputs from the XOR gates 1925 a . . . d act as select signals forthe respective multiplexers 1915 a . . . d to choose one of thepresented normalised path metrics. Each of the multiplexers 1915 a . . .d presents an output to a corresponding one of multiplexers 1910 b 1,1910 d 1, 1910 f 1 and 1910 h 1.

[0147] Multiplexers 1910 a 3 . . . d 3 an 1915 a . . . d are presentedwith different pairs of inputs depending on the values of theLogLikelihood Enable 1214 and the LogLikelihood Enable 0 1203 ₀ andLogLikelihood 1 Enable 1203 ₁. LogLikelihood 0 Enable 1203 ₀ is enabledfor LogLikelihood Processor 0 and disabled for LogLikelihoodProcessor 1. Conversely, LogLikelihood 1 Enable 1203 ₁ is enabled forLogLikelihood Processor 1 and disabled for LogLikelihood Processor 0. Asthe Reverse Address Processor 1270 is used in several locations withinthe unified decoder 1200, the Reverse Address Processor 1270 must becapable of handling different modes of operation. When the LogLikelihoodEnable 1214 and LogLikelihood Enables 1203 ₀ and 1203 ₁ are inactive,the Reverse Address Processor 1270 is in Viterbi mode operating on atrellis generated by a non-systematic convolutional code. WhenLogLikelihood Enable 1214 is active, the Reverse Address Processor 1270is performing reverse trellis switching for the LogLikelihood operationfor LogMAP decoding. When either of the LogLikelihood Enables 1203 ₀ and1203 ₁ is active with the LogLikelihood Enable 1214 active, the ReverseAddress Processor 1270 is performing switching appropriate for aLogLikelihood operation using a recursive systematic code, as in Turbodecoding. The XOR gates implement the appropriate switching for thedifferent operating modes of the Reverse Address Processor 1270.

[0148] Each of the first bank of multiplexers 1910 a 3 . . . 1910 d 3produces an output which is presented to a corresponding latch 1910 a 2. . . 1910 d 2. Each of the latches 1910 a 2 . . . 1910 d 2 receives thereverse trellis hold 1224 as an input and presents a delayed output asthe second input to a corresponding one of the multiplexers 1910 a 1,1910 c 1, 1910 e 1 and 1910 g 1.

[0149] The reverse trellis transparent bit 1226 is broadcast to each ofa third bank of multiplexers 1910 a 1 . . . 1910 h 1, which producecorresponding path metrics 1265 a . . . h. The path metrics 1265 a . . .1265 h are collated and presented as reverse trellis path metrics 1265,the output of the Reverse Address Processor 1270. When the decoder 1200is operating in the forward trellis direction, the reverse trellistransparent bit 1226 is set such that the Reverse Address Processor 1270allows the normalised path metrics 1275 to pass through to become thereverse trellis path metrics 1265, without alteration.

[0150]FIG. 13 shows Normalisation Subtractors 1278 of FIG. 4. Thenormalising output 1246 is presented as an input to each of thesubtractors 1610 a . . . 1610 h. The output 1277 of the bank ofmultiplexers 1278 a is presented as individual path metrics 1277 a . . .1277 h, each of which is presented to corresponding subtractors 1610 a .. . 1610 h. The outputs 1275 a . . . h of the subtractors 1610 a . . .1610 h form the normalised path metrics 1275. The normalisingsubtractors 1278 are used to subtract the maximum path metric,calculated during the traversal of the trellis and presented as thenormalising output 1246, from the new path metrics to ensure that thepath metric values are retained within the dynamic range of thearchitecture.

[0151]FIG. 14 shows a comparator 1247 of FIG. 4, in accordance with apreferred embodiment of the invention. The butterfly path metricspresented on bus 1267 are fanned out to produce inputs 1267 a . . . 1267d to corresponding maximum comparators 1710 a . . . 1710 d. Similarly,the butterfly path metrics presented on bus 1266 are fanned out toproduce inputs 1266 a . . . 1266 d to corresponding maximum comparators1710 e . . . 1710 h. The path metrics 1266 a . . . 1266 d and 1267 a . .. 1267 d are compared against one another and a maximum path metric 1715is output to a multi-row comparator tree, shown in FIG. 17, which spansthe decoder when operated in a multi-row configuration so as to capturethe maximum path metric being calculated for the state of the trellisbeing investigated. An output 1716 from the multi-row comparator tree ispresented to a register 1720, which stores the greatest path metriccalculated during the traversal of the trellis. The output 1716 is alsopresented as an input to a subtractor 1730. The register 1720 provides asecond input to the subtractor 1730, the input being the greatest pathmetric calculated thus far during the traversal of the trellis. Thesubtractor compares the greatest path metric calculated during thetraversal of the trellis with the maximum path metric 1715 and if themaximum path metric 1715, which has just been calculated, is greaterthan the greatest path metric calculated during the traversal of thetrellis, a load signal 1735 is enabled to the register 1720 so that themaximum path metric 1715 is loaded into the register 1720 to become thegreatest path metric calculated during the traversal of the trellis. Theregister provides a further output, being a normalising output 1246,which is fed to the normalising subtractors 1278 and to the IntermediateDecoding Memory and Processor 1240. The normalising output 1246 is usedto ensure that calculated path metric values remain within the dynamicrange of the architecture.

[0152]FIG. 15 shows a path metric memory 1280 of FIG. 4, in accordancewith a preferred embodiment. A path metric reset 1230 and path metricread/write clock 1231 are presented to each of the memory units 1810 a .. . 1810 h. The upper memory blocks 1810 a . . . 1810 d are clustered asB0, and receive an input ADDR0 1228 a. Conversely, the lower memoryblocks 1810 e . . . 1810 h are clustered to form B1, and receive acorresponding input ADDRI 1228 b. The path metric store 1280 receivesthe forward trellis path metrics 1285, which fan out and provide a pathmetric 1285 a . . . 1285 h to each of corresponding memory blocks 1810 a. . . 1810 h, as shown in the diagram. The path metric store 1280buffers the forward trellis path metrics 1285 for one trellis processingcycle and then produces outputs 1276 a . . . 1276 h, which areaggregated and form the stored path metrics 1276.

[0153]FIG. 16 shows a Forward Address Processor 1290 of FIG. 4, inaccordance with a preferred embodiment of the present invention. TheForward Address Processor 1290 provides facilities for delaying andordering path metrics to produce a desired pattern of path metrics. TheForward Address Processor 1290 is also capable of acting transparentlywhen the decoder 1200 is operating in reverse trellis mode such thatinput path metrics are presented as outputs without alteration. Theupper path metric bus 1296 is broken into its component path metrics1296 a . . . 1296 d, which are presented, as indicated, to twomultiplexers 2010 a and 2010 b, each of the multiplexers receiving twoinput path metrics. The lower path metric bus 1295 is broken into itsconstituent path metrics 1295 a . . . 1295 d and presented, asindicated, to two multiplexers 2010 c and 2010 d, each of themultiplexers receiving two input path metrics. The multiplexers 2010 a .. . 2010 d each receive a forward trellis select 1232, which indicateswhich of the presented path metrics 1296 a . . . 1296 d and 1295 a . . .1295 d is to be selected.

[0154] Each of the multiplexers 2010 a . . . 2010 d feeds into acorresponding hold register 2015 a . . . 2015 d. The hold registers 2015a . . . 2015 d each receive an input, being forward trellis hold 1234.The purpose of the multiplexers 2010 a . . . 2010 d and the holdregisters 2015 a . . . 2015 d is to delay certain of the path metrics1296 a . . . 1296 d and 1295 a . . . 1295 d by a clock cycle as part ofthe in-place path metric addressing.

[0155] Each of the hold registers 2015 a . . . 2015 d produces an outputwhich is presented to a bank of multiplexers 2020 as indicated. Theother inputs to the bank of multiplexers 2020 are the constituent pathmetrics of the upper path metric bus 1296 and the lower path metric1295, also as shown. A path metric input multiplexer select 1238 isbroadcast to the bank of multiplexers 2020. The bank of multiplexers2020 produces outputs to a second bank of multiplexers 2030, whose otherinputs are the constituent path metrics of upper path metric bus 1296and lower path metric bus 1295. A forward trellis transparent bit 1236is provided to the second bank of multiplexers 2030 and is used toeffect a transparent path when the decoder 1200 is operating in thereverse trellis mode. The bank of multiplexers 2030 produces pathmetrics 1285 a . . . 1285 h, which are collated to form the forwardtrellis path metrics 1285, being the output of the Forward AddressProcessor 1290.

[0156]FIG. 17 shows the Comparator 1247 of FIG. 4, when used in an eightrow decoder configuration. The comparators 1247′ in each of the rows areinterconnected via a bank of multiplexers 2110. Each multiplexer 2110presents a single input 1716 to a corresponding comparator 1247′ in itscorresponding decoder row. Pairs of comparators 1247′ present theiroutputs 1715 as inputs to ACS node units 1420 a″, 1420 b″, 1420 c″ and1420 d″, each of which spans two rows of the decoder. The outputs 1715of the comparators 1247′ are also presented as recursive inputs to thebank of multiplexers 2110. The ACS nodes units 1420 a″, 1420 b″, 1420 c″and 1420 d″ are paired and present their outputs as inputs to furtherACS nodes units 1430 a″ and 1430 b″. The outputs of the ACS node units1420 a″, 1420 b″, 1420 c″ and 1420 d″ are also presented as recursiveinputs to the bank of multiplexers 2110. The ACS node units 1430 a″present their outputs to a final ACS node unit 1440″ and as recursiveinputs to the bank of multiplexers 2110. The output of the final ACSnode unit 1440″ is presented as a final recursive input to the bank ofmultiplexers 2110. Each multiplexer 2110 is presented with a selectsignal.

[0157]FIG. 18 shows the configuration of the Input Symbol History 1298,including an address controller, of FIG. 4. An Input Symbol HistoryAddress 1219 is presented as an input to a Window Decoder 2210, whichdecodes the address to enable access to a first double buffered memorybank-0 2216 and a second double buffered memory bank-i 2218. The InputSymbol History 1298 double buffers received input to ensure that acontinuous data flow is maintained. Input Symbol History clock 1223 andInput Symbol History reset 1225 are presented to a counter 2212, whoseoutput 1297 a is also presented to the double buffered memory bank-02216 and the double buffered memory bank-1 2218. Input symbols 1299 arepresented from a host processor to a demultiplexer 2214. Thedemultiplexer 2214 produces an output 2224 to double buffered memorybank-0 2216 and the second output 2226 to a double buffered memorybank-1 2218. The demultiplexer 2214 also receives as an input aread/write signal 1297 b. The read/write signal 1297 b also feeds afirst multiplexer 2220 and a second multiplexer 2222. Each of the doublebuffered memory banks 2216 and 2218 is presented with a bank selectsignal 1211, with the bank select signal 1211 being inverted at theinterface to double buffered memory bank-1 2218.

[0158] Double buffered memory bank-0 2216 produces a first output 2228to the multiplexer 2220 and a second output 2230 to a second multiplexer2222. Double buffered memory bank-1 2218 produces a corresponding firstoutput 2232 which feeds multiplexer 2220 and a second output 2234 whichis presented to the second multiplexer 2222. The first multiplexer 2220produces an output 1291 b which is presented as an input toLogLikelihood processor-0 1250 b. The second multiplexer 2222 producesan output 1291 a which is presented as an input to the butterflyprocessors 1260.

[0159]FIG. 18 also shows an exploded view of the double buffered memorybank-1 2218. Incoming data 2226 is presented to a 1-to-n demultiplexer2240, which also receives a window select, being the output of thewindow decode 2210. N outputs from the demultiplexer 2240 are presentedto n corresponding windows W0 . . . Wn, each of which produces an outputwhich is presented to a first m-to-1 multiplexer 2242 and a secondm-to-1 multiplexer 2244. Each of the m-to-1 multiplexers 2242, 2244 alsoreceives a window select input signal. The first m-to-1 multiplexer 2242produces the output 2232 which is used for the dummy beta calculationsand is destined for the LogLikelihood ratio processor-0 1250 a. Thesecond m-to-1 multiplexer 2244 produces the output 2234, which is usedfor calculating alphas and betas in the branch metric units of thebutterfly processors 1260.

[0160]FIG. 19 shows the LogLikelihood ratio processor 1297 of FIG. 4.The LogLikelihood ratio processor 1297 receives inputs 1245 a and 1245b, which are output from LogLikelihood processor-0 1250 a andLogLikelihood processor-1 1250 b, respectively. The LogLikelihood ratioprocessor 1297 also receives as inputs the extrinsic information 1242,the hard or soft output select 1213, Spreading Input 1243, the TracebackProcess Output 1567 and Scramble Address Data 1286.

[0161] A subtractor 2310 receives the inputs 1245 a and 1245 b,representing the likelihood of a “1” and a “0”, respectively, andproduces an output 2315 which feeds a second subtractor 2320. The output2315 of the subtractor 2310 also feeds a first multiplexer 2330 andforms part of an output 1294. The second input to the subtractor 2320 isthe extrinsic information 1242. The output 2325 of the subtractor 2320is presented to a second multiplexer 2340.

[0162] The Traceback Process Output 1567 is presented as a second inputto the first multiplexer 2330. The hard or soft output select 1213 ispresented as the select input of the multiplexer 2330 and the output ofthe multiplexer 2330 forms the zero bit of the decoded output 1294. Theoutput 2315 of the subtractor 2310 is combined with the leastsignificant bit of the output of the multiplexer 2330 to form amulti-bit decoded output 1294.

[0163] The second multiplexer 2340 receives Scramble Address Data 1286as its second input and Spreading Input 1243 as its select signal. Thesecond multiplexer 2340 produces an output 1293, which is fed from theLogLikelihood ratio processor 1297 to the Intermediate Decoding Resultand Memory 1240.

[0164] The embodiment shown in FIG. 3 operates in a five-phase mode. Asno loglikelihood processors are present, more path metric memory isrequired to store more alphas and betas in the computations performed byLogLikelihood Processors 1250 a and 1250 b in the embodiment of FIG. 4,which operates in a two-phase mode.

[0165] Operation

[0166] The first step in the operation of the decoder 1200 is toinitialise the decoder such that the architecture embodies the requiredconfiguration of either convolutional decoding or turbo decoding. Thevariables available for manipulation include the number of columnsneeded for the trellis size in question, the number of states in thetrellis, the mask for the appropriate number of bits to be used in theaddressing of the columns in the path metric memory and the decisiondepth of the traceback process. The register which holds the winningpath metric for the symbol being processed is initialised and sequentialnumbers are assigned to a register bank whose values are permutedbetween every symbol time to reflect the column address sequencerequired for each trellis operation.

[0167] It is to be noted that the decoder 1200 can operate in either theforward or reverse trellis direction.

[0168] In the case in which the trellis is being navigated in theforward direction, the Reverse Address Processor 1270 is configured tooperate in transparent mode by setting the Reverse Trellis TransparentBit 1226. When navigating the trellis in the forward direction, thesequential numbers are rotated to the left after their first use.

[0169] An iterative process begins by reading the path metrics from thecolumn of the path metric store 1280 B0 and B1 corresponding to thenumber of the iteration. The sequential list of path metrics held in thefirst column of 1280 B0 and 1280 B1 are presented to the butterflyprocessors 1260. The butterfly processors 1260 produce, via the bank ofmultiplexers 1250 c, new path metrics, which are no longer in sequentialdestination state order and are fed into the Forward Address Processor1290. The Forward Address Processor 1290 essentially performs a sortoperation on each column of new path metrics with the resultant effectbeing that the columns in the path metrics memory 1280 B0 and B1represent a set of sequential states when reading down the column.During each column operation, as shown in FIGS. 7A-E, half of the eightnew path metrics are written directly into the path metric store 1280,whilst the remaining new path metrics are written into the holdregisters 2015 a. 2015 d within the Forward Address Processor 1290. Thisalternates between each group of path metrics.

[0170] The navigation through the forward trellis requires a number ofcolumn iterations, being one more than the number of columns needed forthe particular trellis in question. If the number of iteration is even,path metrics from buses 1296A, C, E, G are written into the column ofpath metric store 1280 B0 corresponding to the number of the iteration.Path metrics from the buses 1296B, D, F, H are contemporaneously writteninto the hold registers 2015 a . . . 2015 d of the Forward AddressProcessor 1290.

[0171] If, however, it is an odd iteration, the path metrics from buses1296A, C, E, G are written into the hold registers 2015 a . . . 2015 dof the Forward Address Processor 1290 and path metrics from buses 1296B,D, F, H are written into the column of the path metric store 1280corresponding to the number of the iteration.

[0172] During the column operations, the decision bits 1255 generated bythe ACS units of the butterfly processor 1260 are grouped into a byteand written into the Intermediate Decoding Memory and Processor 1240.The next iteration in the process begins by reading the column addressfrom the path metric store 1280 B0 and B1 corresponding to the number ofthe next iteration. The iterative process continues until the number ofcolumn iterations corresponds to one more than the number of columnsrequired for the trellis being calculated.

[0173] A further write operation is required at the end of the iterativeprocess to transfer the four new path metrics in the hold register ofthe Forward Address Processor 1290. The four new path metrics arewritten into the final column of path metric store memory 1280 B1. Thefinal result is that the new path metrics have been written into pathmetric store 1280 B0 and B1, albeit in a different column order.However, it is to be noted that the order within each column has notchanged.

[0174] When the trellis is being navigated in the reverse direction, thesequential numbers are rotated to the right and then used for the firsttime. A group of four path metrics are fetched from the first column ofpath metrics 1280 B0 and are placed in the holding registers within theReverse Address Processor 1270. The Forward Address Processor 1290 isconfigured to operate in a transparent mode by setting the forwardtrellis transparent bit 1236. The corresponding reverse trellistransparent bit 1226 is set such that Reverse Address Processor 1270 isenabled. The navigation through the reverse trellis is described inFIGS. 8A-8F.

[0175] Navigating the trellis in the reverse direction requires a numberof iterations corresponding to one more than the number of columnsrequired for the particular trellis. When navigating the trellis in thereverse direction, the in-place path metric system always presents ascrambled list of path metrics through the Reverse Address Processor1270 to produce a non-sequential list of path metrics to the butterflyprocessors 1260. The resultant trellis state ordering produced by thebutterfly processors 1260 is trellis state sequential.

[0176] In the event that an even iteration is being undertaken, thecolumn in the path metrics store 1280 B0 corresponding to the number ofiterations plus one is read and passed through the multiplexers 1278 a,normalising processors 1278 and the Reverse Address Processor 1270 tothe butterfly processors 1260. The path metrics currently held in theReverse Address Processor 1270 are also read into the butterflyprocessor 1260. The column in path metric store 1280 equivalent to thenumber of the iteration is read and written into the hold register ofthe Reverse Address Processor 1270.

[0177] In the case that the number of the iteration is odd, the columnof path metric store 1280 B1 corresponding to the number of theiteration plus one is read and passed through the multiplexers 1278 aand normalising processors 1278 to the Reverse Address Processor 1270and then to the butterfly processor 1260. The path metrics held in theReverse Address Processor 1270 are also presented as inputs to thebutterfly processor 1260. The column of path metrics store 1280 B0corresponding to the number of the iteration is read and written intothe hold register of the Reverse Address Processor 1270.

[0178] At this point of the navigation of the reverse trellis, thesequential list of path metrics held in the first column of path metricstores 1280 B0 and B1 is presented to the Reverse Address Processor1270. The Reverse Address Processor 1270 performs a sort operation oneach column of new path metrics to the effect that the resultant columnspresented to the butterfly processor 1260 are no longer in sequentialdestination state order. The butterfly processor 1260 produces eight newpath metrics, which are presented, via a bank of multiplexers 1250 c, tothe Forward Address Processor 1290. The Forward Address Processor 1290is in transparent mode , so the trellis-state sequential list of pathmetrics produced by the butterfly processors 1260, via the bank ofmultiplexers 1250 c, is written back into the path metric stores 1280 B0and B1. The path metrics stores 1280 B0 and B1 represent a set ofsequential states when reading down the column.

[0179] During the column operations, the decision bits 1255 generated bythe ACS units of the butterfly processors 1260 are grouped into a byteand presented to the Intermediate Decoding Memory and Processor 1240.The next iteration commences by reading the appropriate column of pathmetrics from path metric stores 1280 B0 and B1.

[0180] At the conclusion of the iterative process, the new path metricsare back in path metrics store 1280 B0 and B1, albeit in a differentcolumn order. It is to be noted that the ordering within each column hasnot changed.

[0181] The traceback processor 1510 within the Intermediate DecodingMemory and Processor 1240 knows the trellis processing direction and thebit location of the decision bit as it performs the well known pointerbased traceback operation. The decision bit is extracted from one byteand is used to generate the next pointer into the traceback memory 1530.Traceback terminates when a predefined traceback depth has beenachieved. The traceback depth is typically between five and nine timesthe constraint length of the code.

[0182] When the decoder 1200 is being used for turbo decoding, theprocessing is broken into two distinct phases: dummy-beta/alphaprocessing and beta/LLR processing. When either the forward trellis orthe reverse trellis operation is mentioned the above processing occurs,but only for the degenerate case of when the number of trellis statesmatches the number of ACS units ACS0 . . . ACS7 in a multiple (power of2) of the ACS unit size of the butterfly processors 1260. TheLogLikelihood processor-0 1250 a and the ACS units within the butterflyprocessor 1260 are each equipped with registers to allow the respectiveACS units to accumulate results needed for alpha and beta calculations.

[0183] The calculation of dummy-betas and alphas occur in parallel. TheLogLikelihood processor-0 1250 a performs a dummy beta calculation usingthe leaf ACS units at its disposal. This calculation requires access tothe input symbol history buffer and the Intermediate Decoding Memory andProcessor interleaver memory, each of which is a windowed memory system.The input symbol history buffer is organised into banks 2216 and 2218 ofthe size of a processing window. The LogLikelihood processor-0 1250 aaccumulates dummy betas by processing at time t the window to beprocessed at time t+1. The LogLikelihood processor-0 1250 a does notneed to access the path metric stores 1280, which is why theLogLikelihood ratio processor-0 1250 a can operate in parallel to theACS units contained within the Butterfly processors 1260.

[0184] The LogLikelihood ratio processor-0 1250 a performs normalisationon the dummy beta values by using the adders in the ACS tree todetermine the maximum beta calculated. This value is then subtractedfrom the inputs to the leaf ACS units of the LogLikelihood ratioprocessor-0 1250 a before they are used.

[0185] The butterfly processors 1260 perform alpha computations,accumulating alpha values in the registers contained within constituentACS units. The butterfly processors 1260 perform the forward trellisoperation and normalisation as is usual during the forward trellisnavigation.

[0186] The dummy betas calculated by the LogLikelihood ratio processor-01250 a are presented to the butterfly processors 1260 at the start ofthe beta calculation phase.

[0187] During calculation of the betas, both LogLikelihood processors1250 a and 1250 b are used in conjunction with the butterfly processors1260. Each of the LogLikelihood processors 1250 a, 1250 b accepts alphasfrom the path metric store 1280, betas resulting from the previous clockcycle and extrinsic information 1242 produced from the IntermediateDecoding Memory and Processor 1240 to create a LogLikelihood result fora “1” and “0”, respectively. The LogLikelihood calculations can spanmultiple rows since they are determining the maximum result over all thestates.

[0188] Beta computations work in the reverse direction through the inputsymbol history window, compared to the alphas, and use gammas used inthe alpha calculations. The beta computations use the same trellisbranch metric assignments that were used for the alpha calculations.

[0189] When the whole block of input history has been processed and theresultant outputs have been fed into the interleaver 1520, the processis able to commence for the second half of the turbo decoder operation.The interleaver operation during first decoder operation is readsequentially and written sequentially. During second decoder operation,the interleaver is read from and written to, albeit using the randomaddress sequence as determined by the scrambler address output. Duringsecond decoder operation, the read and write addresses are the same. Theinterleaver operation after the first decoder writes in sequentially andreads out randomly, as per the predefined spreading sequence which isused to give the first and second decoders their statisticalindependence. The interleaver operation for the second decoder writesrandomly, as per the spreading sequence, and reads sequentially.

[0190] It is to be noted that because the encoders used for turboencoding do not have to be the same, the decoding rates and constraintsof the second decoder need not necessarily be the same as those for thefirst decoder. This may require that the configuration of the turbodecoder be changed between block processing operations. If this is thecase, it is easily dealt with by manipulating the contents of theconfiguration registers.

[0191] Each block of input symbol history requires several completeturbo iterations in order to be decoded to within an acceptable biterror rate. The number of iterations required is configurable to ensurethat the required bit error rate is achieved.

[0192] A benefit of the architecture in question is that it onlyrequires two phases to complete one turbo decode iteration. Thisprovides flexibility in the use of the architecture and allows thenumber of decoder rows used to be traded for the number of iterationsrequired. For example, a turbo decoder that does four iterations may beimplemented using two decoder rows requiring two iteration times.

[0193] LogMAP computation is performed using a sliding window algorithm.The sliding window algorithm is implemented in 2 phases. In a singledecoder this results in increased latency: 2 passes over each window asshown in the configuration (with only a single decoder being used) inFIG. 20A. The first pass computes the dummy beta values and the forwardalpha values in parallel and stores the forward alpha values in thealpha memory (NOTE: this memory is the same memory as used in theViterbi algorithm for path metric storage). The second pass reads thealpha values and computes the beta values according to the LogMAPalgorithm and outputs LogLikelihood ratios (LLR).

[0194] When multiple decoders are used, the computation of the twophases can be overlapped and the decoder can process a single block withreduced latency. Multiple decoders can operate separately on differentdata streams or they can co-operate to increase the decoding speed of asingle stream, as shown in the configuration of FIG. 20B. Theimplementation shown in FIG. 3 can process 4 independent streams or 2streams with increased speed (and reduced latency) or 1 stream withfurther increased speed (and minimal latency).

[0195] Table 1 demonstrates the flexibility of the unified decoder tosupport multiple encoded streams simultaneously. For example, a decoderwith 4 decoder rows can process up to 4 data streams at the same time.Furthermore, the decoder rows can operate together to decode fewerstreams at higher throughput. This is useful for minimizing the latencyof voice decoding. Table 1 demonstrates the flexibility of this approachand the appropriate decoding speed-up obtained in each case. (Again—thislist is by no-means complete—more decoder rows can be connected togetherto achieve even greater flexibility.) TABLE 1 Example decodingconfigurations of multi-bank interconnected decoders. Decoding Speed-Up(over convolutional/ Scenario Decoder Configuration turbo on 1 decoder)1 convolutional 4 decoders per stream 4X (conv) 2 convolutional 2decoders per stream 2X (conv), 2X (conv) 3 convolutional 1 decoder for1X (conv), 1X (conv), 2 streams, 2 decoders for 2X (conv) 1 stream 4convolutional 1 decoder per stream 1X, 1X, 1X, 1X 1 turbo 2 decoders perstream 2X (turbo) 2 turbo 1 decoder per stream 1X, 1X 4 turbo 1 decoderper stream 1X, 1X, 1X, 1X 1 convolutional & 1 decoder conv, 1X (conv),2X (turbo) 1 turbo 2 decoders turbo

[0196] To demonstrate how 2 or 4 decoders can co-operate to decode fewerdata streams at a higher speed, FIG. 21 shows the interconnectionsbetween two decoders. The boxes marked “M” are multiplexers that enablesome of the path metrics from adjacent decoders to be swapped beforewriting to the path metric memories. In this manner, the decoders canoperate as a single decoder. Furthermore, FIG. 22 shows how 4 decoderscan be interconnected to function as either a single decoder, twoseparate decoders, or 4 separate decoders.

[0197] To demonstrate the multi-standard nature of the unified decoder,the decoder can support any combination of the standards shown in Table2. (This list is by no means complete—but is included to demonstrate theflexible (and therefore useful) nature of this unified decoder). TABLE 2Example of standards supported by unified decoder. Standard Code RateConstraint Length GSM - full-rate voice ½ 5 GSM - half-rate voice ⅓ 7GSM - data full-rate (9.6 Kbps) ½ 5 GSM - data full rate (4.8 Kbps) ⅓ 5GSM - data full rate (2.4 Kbps) ⅙ 5 GPRS - CS-1 ½ 5 EDGE - MCS (1-9) ⅓ 7GSM-AMR TCH/AFS6.7 ¼ 7 GSM-AMR TCH/AFS5.15 ⅕ 7 UMTS Voice (slotted) ½ 9UMTS Voice (normal) ⅓ 9 UMTS Data (Turbo) ½ 4 UMTS Data (Turbo) ⅓ 4 CDMA2000 Voice ½ 9 CDMA 2000 Voice ¼ 9 CDMA 2000 Data (Turbo) ¼ 4

[0198] The unified decoder 900 implements the decoding required forconvolutional encoded and turbo encoded data streams and can supportmultiple data streams and multiple voice streams simultaneously. Whendecoding Turbo-encoded data streams, this decoder implements aniterative Turbo decoder using either the MAX-LOG MAP or the LOG-MAPsoft-output MAP algorithms. The decoder maximizes the re-use of itscomponents to enable the efficient implementation of both convolutionaland turbo decoding systems.

[0199] The decoder can be dynamically partitioned, as required, todecode voice streams for different standards. The decoder can processstreams with different coding rates (rate {fraction (1/2)}, rate{fraction (1/3)}, rate {fraction (1/4)}, etc.). It can also processstreams encoded with different constraint lengths. As such, the unifieddecoder architecture is capable of supporting each of the mobilewireless standards currently defined: first, second and third generationfor both voice and data.

[0200] The unified decoder architecture of the preferred embodimentencapsulates the functionality of non-systematic (feed forward) encodersand systematic encoders (feed backward) in a single architecture. FIG.23A shows mixing of polynomials 3240 and state bits 3250 to produce asingle code bit 3225_0 of a code word 3225. Polynomials 3240 arepresented to corresponding AND gates 3260, which also receive states3250 as inputs. Each of the AND gates 3260 produces an output to acorresponding XOR gate 3270. Each XOR gate 3270 also receives aTRANSITION INPUT 3280 and produces an output 3225_0 of the M-bitnon-systematic encoder 3230.

[0201]FIG. 23B shows a whole encoder 3200 for a code word 3225.Polynomials 3240 are presented to corresponding M-bit non-systematicencoders 3230. An input bit 3220 is presented to an XOR gate 3275. ARSC_ENABLE signal is presented to an AND gate 3280, the output of whichis the second input of the XOR gate 3275. The AND gate 3280 alsoreceives as an input the output of the encoders 3230. The XOR gate 3275presents an output to an M-bit shift register 3210 and to each of theencoders 3230. The M-Bit Shift Register 3210 also receives a clocksignal 3285 and a reset signal 3290 and holds a state of the encoder3200 at a time T. The state value is used in conjunction with eachparticular polynomial 3240 (as specified by a particular code) toproduce a non-systematic code bit. The output 3250 of the register 3210is broadcast to each of the encoders 3230. The outputs 3225_0 . . .3225_R of the encoder 3230 are collated to form the CODE_WORD 3225.

[0202] By enabling the RSC_ENABLE 3215, the encoder 3200 becomes arecursive, systematic (RS) encoder. In a recursive, systematic code, theinput bit 3220 forms the systematic bit of a code word 3225. Thegenerated bits of each M-Bit Encoder 3230 form the remainder of the RScode word 3225.

[0203] In the case of a non-systematic encoder the CODE_WORD 3225 wouldcontain R bits (where R=the rate of the code). When the RSC_ENABLE 3215is active, the CODE_WORD 3225 is typically 1-bit wide. The outputCODE_WORD 3225 (in this case 1-bit wide) and the INPUT_BIT 3220 form theRS code word.

[0204] It is apparent from the above that the embodiment(s) of theinvention are applicable to the decoding of multiple wirelesstransmission standards using a unified, scalable architecture.

[0205] The foregoing describes only one embodiment/some embodiments ofthe present invention, and modifications and/or changes can be madethereto without departing from the scope and spirit of the invention,the embodiment(s) being illustrative and not restrictive.

We claim:
 1. A reconfigurable architecture for decoding datacommunications signals transmitted according to one of a plurality ofcoding schemes, said coding schemes comprising convolutional and turbocodes, said architecture comprising: a trellis processing arrangementfor receiving an input signal derived from said transmitted signals andnew path metrics for determining intermediate decoded results using saidnew path metrics; an intermediate store for receiving modified decodedresults and for providing a decoded output; and control processor meanscoupled to said trellis processing arrangement and operable to configuresaid architecture for one of convolutional or turbo decoding by (i)developing said new path metrics using generated path metrics outputfrom the trellis processing arrangement, (ii) determining said modifieddecoded results from said intermediate decoded results, and (iii) fordetermining said decoded output from a selected one of said modifieddecoded results.
 2. A reconfigurable architecture as claimed in claim 1,wherein when said control processor means configures said architecturefor convolutional decoding using a Viterbi algorithm, said new pathmetrics comprise said generated path metrics, said intermediate decodingresults comprise decision bits from said trellis processing arrangement,and said intermediate store and said control arrangement implementtraceback processing of said intermediate decoded results to provide aconvolutionally decoded output.
 3. A reconfigurable architecture asclaimed in claim 2, wherein said trellis processing arrangementcomprises: butterfly processor means configured for receiving said inputsymbol and for generating intermediate decoded results and generatedpath metrics; a first path metric store for providing old path metricsto said butterfly processor means; and a second path metric store forreceiving new path metrics and buffering said new path metrics to saidfirst path metric store.
 4. A reconfigurable architecture as claimed inclaim 1, wherein when said control processor means configures saidarchitecture for convolutional decoding using a LogMAP algorithm, saidtrellis processing arrangement implements LogMAP trellis processing andsaid intermediate store forms part of a store within said trellisprocessing arrangement.
 5. A reconfigurable architecture as claimed inclaim 4, wherein said trellis processing arrangement comprises:butterfly processor means configured for receiving said input symbol andfor generating intermediate decoded results and generated path metrics;a first path metric store for providing old path metrics to saidbutterfly processor means; and a second path metric store for receivingnew path metrics and buffering said new path metrics to said first pathmetric store.
 6. A reconfigurable architecture as claimed in claim 5,wherein said intermediate store forms part of said first path metricstore.
 7. A reconfigurable architecture as claimed in claim 5, whereinsaid first and second path metric stores are formed by a double bufferedmemory arrangement.
 8. A reconfigurable architecture as claimed in claim5, wherein said first and second stores comprise registers.
 9. Areconfigurable architecture as claimed in claim 5, wherein said secondpath metric store is formed using a plurality of hold registers, saidarchitecture further comprising a multiplexer arrangementinterconnecting said hold registers and said first path metric store,said multiplexer arrangement being configurable by said control sprocessor means to update said first path metric store with aspecifically ordered sequence of said new path metrics supplied to saidhold registers in an originating sequence.
 10. A reconfigurablearchitecture as claimed in claim 1, wherein when said control processormeans configures said architecture for turbo decoding, said intermediatedecoding results comprise extrinsic information that is modified by saidcontrol processor means using interleaving, and said trellis processingarrangement implementing LogMAP trellis processing to produce newextrinsic information supplied to said intermediate store, to provide aturbo decoded output.
 11. A reconfigurable architecture as claimed inclaim 10, wherein said trellis processing arrangement comprises:butterfly processor means configured for receiving said input symbol andfor generating intermediate decoded results and generated path metrics;a first path metric store for providing old path metrics to saidbutterfly processor means; and a second path metric store for receivingnew path metrics and buffering said new path metrics to said first pathmetric store.
 12. A reconfigurable architecture as claimed in claim 11wherein said intermediate store forms part of said first path metricstore.
 13. A reconfigurable architecture as claimed in claim 11, whereinsaid first and second path metric stores are formed by a double bufferedmemory arrangement.
 14. A reconfigurable architecture as claimed inclaim 11, wherein said first and second stores comprise registers.
 15. Areconfigurable architecture as claimed in claim 11, wherein said secondpath metric store is formed using a plurality of hold registers, saidarchitecture further comprising a multiplexer arrangementinterconnecting said hold registers and said first path metric store,said multiplexer arrangement being configurable by said controlprocessor means to update said first path metric store with aspecifically ordered sequence of said new path metrics supplied to saidhold registers in an originating sequence.
 16. A telecommunicationsdecoding device comprising: a parallel arrangement of decodingprocessors and at least one store each arranged in a process loopconveying decoding process values received by and generated from saiddecoding processors; wherein said decoding processors receive coded dataand present decoded results, and a flow of said decoding process valuesabout said process loop is controlled to alter a decoding functionperformed by said device from one decoding scheme to at least one otherdecoding scheme.
 17. A telecommunications decoding device according toclaim 16, wherein said process loop comprises said decoding processorsfor generating path metrics in a first time period for retention in saidstore, said store presenting said path metrics to said decodingprocessors in a following time period.
 18. A telecommunications decodingdevice according to claim 17, wherein said process loop furthercomprises at least one address processor configured to alter a generatedorder in which said path metrics are generated by said decodingprocessors to a supply order by which said path metrics are supplied tosaid decoding processors.
 19. A telecommunications decoding deviceaccording to claim 18 wherein said address processor comprises anintermediate store and switching arrangement arranged between saiddecoding processors and said at least one store.
 20. Atelecommunications decoding device according to claim 18 wherein saidaddress processor comprises an intermediate store and switchingarrangement arranged between said at least one store and said decodingprocessors.
 21. A telecommunications decoding device according to claim19 or 20 wherein said intermediate store provides a delay of said firsttime period to said path metrics as determined by a predetermined pathmetric pattern established by said control arrangement.
 22. Atelecommunications decoding device according to claim 21 wherein saidtrellis processor comprises first, second and third bank of multiplexersand said intermediate store, each of said banks receiving path metricsgenerated from said decoding processors, said first bank presentingselected path metrics to said intermediate store, said intermediatestore delaying the selected path metrics and presenting the selectedpath metrics to said second bank in the further time period, said secondand third banks configured by said control arrangement to present apredetermined sequence of said path metrics and said selected pathmetrics to said first store.
 23. A telecommunications decoding deviceaccording to claim 21 wherein said trellis processor comprises first,second and third bank of multiplexers and said intermediate store, eachof said first and second banks receiving path metrics generated fromsaid first store, said first bank presenting selected path metrics tosaid intermediate store and said third bank of multiplexers, saidintermediate store delaying the selected path metrics and presenting theselected path metrics to said third bank in the further time period,said first, second and third banks configured by said controlarrangement to present a predetermined sequence of said path metrics andsaid selected path metrics to said decoding processors.
 24. Atelecommunications decoding device according to claim 16, wherein saidinput data is encoded using one of convolutional or turbo codes.
 25. Atelecommunications decoding device according to claim 16, wherein saiddecoding processors are butterfly processors.
 26. A telecommunicationsdecoding device according to claim 16, wherein said control arrangementreconfigures a flow of said decoding process values about said processloop to implement convolutional decoding.
 27. A telecommunicationsdecoding device according to claim 16, wherein said control arrangementreconfigures a flow of said decoding process values about said processloop to implement turbo decoding.
 28. A telecommunications decodingdevice according to claim 16, wherein said process loop furthercomprises at least one of a forward address processor and a reverseaddress processor, wherein path metrics generated by said decodingprocessors are presented to said forward address processor, said forwardaddress processor generating outputs presented to said store, said storepresenting outputs to said reverse address processor, said reverseaddress processor presenting outputs to said decoding processors, saidcontrol arrangement enabling one of said forward address processor andsaid reverse address processor according to a desired direction ofevaluation of a coding trellis and said control arrangementreconfiguring said flow of decoding process values to present apredetermined sequence of path metrics to the decoding processors.
 29. Amethod of handling path metrics in a telecommunications decoding deviceconfigured for decoding one of convolutional and turbo codes, saidmethod comprising the steps of: storing new path metrics generated aspart of a decoding process; and providing the stored path metrics to areverse address processor for altering a pattern of said path metrics tobe provided to decoding processors that generate said new path metricssupplied to a forward address processor, the forward address processoroutputting said path metrics to said store, wherein during one offorward trellis decoding and reverse trellis decoding the complementingreverse address processor and forward address processor is disabled fromthe corresponding altering function.
 30. A reconfigurable architecturefor decoding data communications signals transmitted according to one ofa plurality of coding schemes, said coding schemes comprisingconvolutional and turbo codes, said architecture comprising: a symbolhistory means for receiving an input symbol derived from saidtransmitted signals to be decoded and for providing a buffered inputsymbol delayed by a predetermined period; a butterfly processorconfigured for receiving said input symbol and for generatingintermediate decoded results and new path metrics from said input symboland old path metrics; comparator means for receiving said new pathmetrics and determining a greatest path metric obtained during acalculation of a column of a decoding trellis by said butterflyprocessor; a traceback and interleaver processor for receiving saidgreatest path metric and said decoded results; a first bank ofmultiplexers arranged to receive said new path metrics and log outputsfrom a first LogLikelihood processor and to output one thereof asprocess metrics; said process metrics being supplied to each of saidfirst LogLikelihood processor and a second LogLikelihood processor, saidfirst LogLikelihood processor receiving said buffered input symbol, eachof said LogLikelihood processors determining a log-likelihood value,said values being supplied together with outputs of said traceback andinterleaver processor to a LogLikelihood ratio processor for providing adecoded output for said input symbol from said architecture; saidprocess metrics being further supplied to a processing chain configuredto provide said old path metrics to said butterfly processor, saidprocessing chain comprising a forward trellis processor for orderingsaid process metrics into a path metrics store, a second bank ofmultiplexers for selecting path metrics from said store or said processmetrics for supply to a normalising processor also input with saidgreatest path metric, and a reverse trellis processor for receiving anoutput of said normalising processor to order normalised path metrics toform said old path metrics; and a control arrangement coupled to each ofsaid symbol history means, said butterfly processing means, saidcomparator means, said first bank of multiplexers, said firstLogLikelihood processor means, said second LogLikelihood processormeans, said traceback and interleaver processor, said LogLikelihoodratio processor, said forward trellis processor, said path metricstores, said second bank of multiplexers, said normalising processor andsaid reverse trellis processor, said control arrangement being operableto configure said architecture for one of convolutional or turbodecoding according to one of a forward trellis coding or a reversetrellis coding.
 31. A reconfigurable architecture as claimed in claim30, wherein said control arrangement receives a plurality of controlinputs comprising: a coding rate of said input symbols indicating howmuch information is used to represent a single data bit presented in atransmitted block; a constraint length specifying the complexity oftrellis to be decoded: polynomials for use by said butterfly processorand said LogLikelihood processors, the polynomials corresponding to aspecific one of coding schemes; a number of iterations for turbodecoding; a block length for defining how much data is to be processed;a clock signal; and a reset signal; wherein said received control inputsare used by said control arrangement to configure said architecture. 32.A reconfigurable architecture as claimed in claim 30, wherein saidnormalising processor receives said greatest path metric from saidcomparator means and subtracts said greatest path metric from pathmetrics received from said path metrics store to ensure that said newpath metrics are retained within a dynamic range of said architecture.33. A reconfigurable architecture as claimed in claim 30, wherein saidfirst and second banks of multiplexer provide points of interconnectionto a further one or more of said reconfigurable architecture for one ofscaled or multiple decoding.
 34. A reconfigurable architecture asclaimed in claim 30, wherein said decoded output is a soft decisionoutput when said architecture is configured for turbo decoding.
 35. Areconfigurable architecture as claimed in claim 30, wherein said decodedoutput is a hard decision output when said architecture is configuredfor convolutional decoding using a Viterbi algorithm.
 36. Areconfigurable architecture as claimed in claim 30, wherein said decodedoutput is a soft decision output when said architecture is configuredfor convolutional decoding using a LogMAP algorithm.
 37. Areconfigurable architecture as claimed in claim 30, wherein saidarchitecture is capable of outputting a maximum accumulated path metric.38. A reconfigurable architecture as claimed in claim 30, wherein saidarchitecture is capable of outputting a minimum accumulated path metric.39. A reconfigurable architecture as claimed in claim 30, wherein saidarchitecture is capable of outputting maximum and minimum accumulatedpath metrics.
 40. A decoder, comprising: a plurality of computationunits, each of said computation units performing a single function;wherein in a first mode of operation, at least a first subset of saidcomputation units are arranged so as to perform decoding of an inputsymbol at a first time according to a first decoding mode, and in asecond mode of operation, at least a second subset of said computationunits, which includes at least one computation unit that was in saidfirst subset, are arranged so as to perform decoding of said inputsignal at a second time according to a second decoding mode.
 41. Atelecommunications decoding device comprising a reconfigurablearchitecture for decoding input data provided according to one of aplurality of coding schemes, said architecture comprising a plurality ofatomic processing units, each said atomic processing unit being coupledvia a binary tree arrangement of switching structures to s provide amodified decoding arrangement producing a single decoded output, saidsingle decoded output being presented recursively via a bank ofmultiplexers as an input to each said atomic unit.
 42. A deviceaccording to claim 1, wherein said coding schemes comprise convolutionalcodes and turbo codes.
 43. A device according to claim 2, wherein wheninput data comprises convolutional codes input to each one of aplurality of said devices, said devices decode said input data over aperiod substantially inversely proportional to the number of saiddevices.
 44. A device according to claim 2, wherein when said input datacomprises turbo codes supplied to each of a plurality of said devices,said devices decode said input data over a period substantiallyinversely proportional to the number of said devices.
 45. A deviceaccording to claim 2, wherein one or more of said atomic processingunits act on different code blocks to improve throughput of thetelecommunications decoding device.
 46. A telecommunications decoder fordecoding input symbols to provide output data, said decoding involvingevaluation of a trellis for each said input symbol, said decodercomprising: a first processor for evaluating said trellis in a firstdirection; a second processor for evaluating said trellis in a seconddirection; and means for enabling operation of one of said processorsaccording to a determined coding arrangement of said input symbols. 47.A telecommunications decoder as claimed in claim 46, wherein said firstand second processors are enabled when performing LogMAP calculations.48. A telecommunications decoder as claimed in claim 46, wherein thesame decoder performs Viterbi calculations.